Unlocking Open Source RISC-V SoC Verification - Michael Gielda

Unlocking Open Source RISC-V SoC Verification - Michael Gielda

While RISC-V has spawned a large number of open source core implementations and energized the open hardware and design tooling community, verification - a major element of any modern SoC design - is still primarily done with proprietary tooling, which prevents the collaborative approach to development we have seen in other areas. CHIPS Alliance takes the RISC-V mission beyond the CPU and into the SoC and tooling domains, and one of our key focus areas has been open source verification using Verilator. The effort, spearheaded by Antmicro, Western Digital and Google, has seen very good progress in the recent months. We will discuss the current capabilities, opportunities and the road ahead for this effort, including dynamic scheduling which is on the way to being merged into Verilator in the upcoming 5.X version, the UHDM SystemVerilog frontend as well as plans for supporting further SystemVerilog constructs and other HDL languages.

[volodymyrdobrovolsky]

The RISC-V is based on 40-year old ideas as RISC-V Foundation claims. There is no sense to port the huge x86 and ARM software ecosystems on it. Thus, RISC-V will never gain a victory over x86 and ARM. The most of positives about the RISC-V processor are arbitrary speculations. The advantage of RISC-V is open architecture. RISC-V has instructions of variable lengths. This is bad, it is a departure from the RISC architecture principles.
The Contemporary microprocessors contain 8 specific hardware components: (1) SMT (Simultaneous Multithreading), (2) register renaming, (3) instruction reordering, (4) out-of-order execution, (5) speculative execution, (6) superscalar execution, (7) delayed branch, (8) branch prediction. These components make up some kind of a “magnificent eight” of components which essentially raise the performance of microprocessors. But unfortunately they are very complex. A processor core having these components is a full-fledged one, otherwise it is good for simple applications, e. g. for embedded systems.
The “magnificent eight” of components is very hard to design, only the experienced firms and developers are able to do this, and much know-how was acquired, some effective solutions are patented. Particularly complex is the SMT. Only powerful and advanced firms like Intel, AMD, IBM are able to equip their processors with the “magnificent eight” components. It is not surprising that some Intel processors, and the famous Apple's M1 processor do not contain SMTs. If a company is able create the full-fledged RISC-V processor with all “magnificent eight” components then it would be a serious achievement, and such RISC-V would be considered of the World's class comparable with x86, with ARM, but not more. As far as I understand most of the developed RISC-V processors have no components from the “magnificent eight”, and are intended for embedded systems.
A course directed on further development of RISC-V is a wrong way, and leads the computer architecture to deadlock. The RISC-V is not promising for computer industry. In fact, RISC-V hampers the further development of the state-of-the-art microprocessor technologies. The World demands absolutely novel microprocessor having much more higher performance than all contemporary ones. The novel and effective ideas on computer architectures do exist! Here’s such a novel processor architecture: V. K. Dobrovolskyi. Microprocessor Based on the Minimal Hardware Principle. Electronic Modeling, 2019, vol 41, No 6. pp. 77-90. The article is posted (under the Cyrillic name добровольский.pdf):
This processor does not have the “magnificent eight”, it is not necessary at all. This comment reflects different view on the RISC-V architecture, and the computer community has a right to become familiar with such a view. I’m Volodymyr Dobrovolskyi (V.K.Dobrovolskyi).