Differences between Cache and Registers (Computer Architecture)

Check this video to know the differences between cache memory and registers!

Link to other videos:

LIKE and SHARE the video.
Comment down your answers.
SUBSCRIBE to the channel!

You can find me on:

Cheers!
#computerarchitecture #cache #coa #computermemory

[BinaBhatt]

Don't forget to subscribe and hit the bell icon!

[guitaraditya]

This is the only video on youtube right now that explains the actual concept in such easy manner.

[andlnull]

Great video but that analogy at the end really brought it home ❤, I need things explained to me like a little baby sometimes 😂

[keshavladha]

This was such an amazing video, the last 15 seconds of analogy summed up everything for me!!

Thank you so much🙏🙏

[kellylang]

Thank you for this quick explanation. The analogy at the end was perfect.

[BannableOffense...]

your explanation on the subject just gave me a way better understanding in the item I was struggling to fully understand, your awesome thank you!

[genericYoutubeUser-tozu]

very well explained and easy to understand. much better than other videos available on youtube

[stachowi]

This was fantastic. I'm an EE/CS... very clearly explained.

[vishalgauswami]

Nice video
Keep working on it. It's very helpful for others.
Thanks.

[vibhu]

Great video with a very clear explanation, thankyou so much you are a great teacher.

[kunalsinghverma]

thankyou so much.. you made understanding easier .. 👍🙏

[k]

A cache should be larger than a register file (i.e. there are many more memory cells in the cache than there are registers, so the signal carrying address of requested cell is 1) longer (for example 16 bits instead of 4 bits) and 2) has to pass more logic gates, mainly multiplexers / demultiplexers, until the signal gets to its destination.

Or maybe it has something to do with cache coherency? Let's say there is some hardware element that ensures coherency of different caches; then there should be times when the cache is locked, because coherency-ensuring element is updating the cache right now, so CPU has to wait until it's over, otherwise it would get incoherent data from the cache.

Or the cache could be implemented with slower and cheaper technology; for example if the registers are built on Nand gates, and the cache is built on capacitors like DRAM. Though I think all CPU cache today is built with logic gates and not capacitors..

[syedyousuffaizan]

Awsome content❤🔥🔥, very well explained. Would it be possible for you to make a similar video on how the data/address actually flow from the memory to cache and to the general purpose register, in detail?

[AuroraLex]

0:45 This was the question I wanted answered

[ldrukhu]

Good analogy and explanation could u give the reaon why registers are ruicker to access compared to cpu cache? (other than physical distance)

[akshaygodase]

Great video!
But why internal cache is faster than external cache?
Is this because, external bus to carry data is slower than internal bus?
Like external is AHB where as internal is AXI?

[soukatdas]

as registers hold a lot amount of data and CPU can access it very fast thats why registers are better that cache

[rsf]

I have Question about RISC.. There is a Difference between Risc and Risc-V??? Plzz Answer this. And make a vedio on Block Diagram of Risc-V.... Plzzz

[reinierkroneman]

You deserve credit for me passing Comptia a+ 🙏🏼

[azazafridi]

Bz the cache memory is highly storage as compare to Registers so its rule that in highly memory fetch data is hard as compared to low memory