Verilog курс с HDLBits! Иерархия модулей в Verilog, сделал модуль в модуле! 2023 12 14

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Видео по теме Verilog практический курс
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Пример что получилось!
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module top_module ( input a, input b, output out );
// Create an instance of "mod_a" named "inst1", and connect ports by name:
// mod_a inst1 (
// .in1(a), // Port"in1"connects to wire "a"
// .in2(b), // Port "in2" connects to wire "b"
// .out(out) // Port "out" connects to wire "out"
// (Note: mod_a's port "out" is not related to top_module's wire "out".
// It is simply coincidence that they have the same name)
);

/*
// Create an instance of "mod_a" named "inst2", and connect ports by position:
mod_a inst2 ( a, b, out ); // The three wires are connected to ports in1, in2, and out, respectively.
*/

mod_a instance2 ( .out(out), .in1(a), .in2(b) );
endmodule
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Продолжение следует...
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