Chip floorplanning with deep reinforcement learning

preview_player
Показать описание
Learn about a deep reinforcement learning method that can generate superhuman chip layouts in under six hours, rather than weeks or months of human effort. This method was recently published in Nature and was used in production to generate chip layouts for Google’s latest AI accelerator (TPU).

Speakers:
Anna Goldie (Staff Research Scientist), Azalia Mirhoseini (Staff Research Scientist)

#MLCommunityDay

product: TensorFlow - General; event: ML Community Day 2021; fullname: Anna Goldie, Azalia Mirhoseini; re_ty: Publish;
  1. TensorFlow
  2. deep reinforcement learning
  3. chip layouts
  4. TPU
  5. Google's AI accelerator
  6. Machine Learning
Рекомендации по теме
Chip floorplanning with 0:09:33

Chip floorplanning with deep reinforcement learning

Chip Placement with 0:27:27

Chip Placement with Deep Reinforcement Learning (Paper Explained)

M4LA 2021 - 0:35:26

M4LA 2021 - Anna Goldie - Model Parallelism and Chip Floorplanning with Deep Reinforcement Learning

Chip Placement with 0:35:41

Chip Placement with Deep Reinforcement Learning | Paper Explained

Reinforcement Learning for 0:57:26

Reinforcement Learning for Hardware Design feat. Anna Goldie | Stanford MLSys Seminar Episode 14

Google brain - 0:00:30

Google brain - AI Chip development for floor planning

Chip Placement with 0:31:52

Chip Placement with Deep Reinforcement Learning #4

Keynote: ML for 0:19:37

Keynote: ML for Systems and Chip Design - Azalia Mirhoseini, Senior Research Scientist, Google Brain

Chip Placement with 0:23:10

Chip Placement with Deep Reinforcement Learning #3

Deep Reinforcement Learning: 0:10:38

Deep Reinforcement Learning: Field Development Optimization | Paper Explained

Google’s AI chief 0:01:14

Google’s AI chief explains machine learning for chip design

New AI Learned 0:12:46

New AI Learned to Design Computer Chips: The View of a Chip Designer

Google-KI übertrifft jeden 0:07:22

Google-KI übertrifft jeden Menschen in Chipentwicklung

Google’s Chip Designing 0:13:18

Google’s Chip Designing AI

Machine-Learning Optimized Chip 0:17:47

Machine-Learning Optimized Chip Design -- Cadence Design Systems

Device Placement Optimization 0:21:35

Device Placement Optimization with Reinforcement Learning

Reinforcement learning for 0:44:35

Reinforcement learning for chip design

Build a board 0:06:11

Build a board game app with policy gradient (Reinforcement learning with TensorFlow Agents)

AI-agents Trained using 0:16:07

AI-agents Trained using Deep Reinforcement Learning in the CARLA Simulator

The Impact Of 0:17:03

The Impact Of Machine Learning On Chip Design

Deep Reinforcement Learning 0:59:25

Deep Reinforcement Learning for Online Combinatorial Optimization: The Case of Bipartite Matching

【Research 01】My research 0:23:19

【Research 01】My research on transition control based on multi-agent deep reinforcement learning

Device Placement Optimisation 0:22:11

Device Placement Optimisation with Reinforcement Learning

State-of-the-art Machine Learning 0:03:41

State-of-the-art Machine Learning research with Google tools | Keynote

Комментарии
Автор

Very impressive! Do you have a experimental db for this or implementation flow?

kumudsingh
Автор

I've always been interested in this type of stuff, but for some reason the EE academic path rarely ventures here, although one would think it did. It seems this is more CS, but most CS people don't care about chip routing. So how do I pursue a degree in this type of thing? AI/ML for system design is inevitable and I wish to play a part.

sonicsmooth
Автор

@tensorflow will you be releasing code for this?

mrinalmathur
Автор

you are using a training data with answers can we call this reinforcement learning??

rg
Автор

You cant build scheme just minimizing wire length, power, etc.
There are many physics processes and limitation that you should take in consideration, especially for radio and medical devices.

So right now you are building more images then production product.

AndreyNikishaev