Associative array in SystemVerilog - Part-1 and working of SystemVerilog foreach loop.

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hi,do you know how to simulate index value of array, such as foreach
in modelsim, display value is ok, but the value shown by [examine] is always wrong. do you know why?

int md[2][3] = '{'{1, 2, 3}, '{4, 5, 6}};
initial begin
foreach(md[i, j])
$display("md[%0d][%0d]=%0d", i, j, md[i][j]);
end

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