TLM Connections in UVM

Показать описание

POPULAR UVM TRAINING

Subscribe to our channel, @DoulosTraining, for more:
- Introductory videos to range of our most popular training topics – System Verilog, UVM, SystemC & TLM-2.0, VHDL, Python & Deep Learning, & Arm.
- Answers to common questions & “how to’s ”.
- Our latest live & on-demand webinars (& joining links).

Follow us on Twitter: @DoulosTraining

Рекомендации по теме

Комментарии

Hi John,
your video is the clearest tutorial I have found in web. It really answered all my confusions.
Thank you!

liyixuan

Thank you so much for this wonderful explanation of this topic which has been haunting me for quite a time now. Now I feel confident with TLM connections in UVM!

harsh

Excellent video. One minor thing for newbies that took me a while to realize: 'imp' stands for 'implementation', and has nothing to do with 'import'.

miklosbence

Excelent video and series in general. Very clear and elucidating explanation of concepts. Congratulations!

jaumm

Excellent video, thanks. Although I find utterly confusing the fact that producer and consumer boxes on top and bottom are swapped for the put and get implementations (07:40). Why not leave the producer on the left and consumer on the right also for the get implementation?

pablom

thanks for the most comprehensive explanation on TLM Connections.

devsamwise

Hii John this video is really great👍 I request you if you can make video about scope resolution operators

rajhanskolhe

Thank you for such clear explanations!

RKishmar

Hi John...i am individual, can i take training from doulos?

syedtaahir

trying to understand why they made analysis ports are so excessively convoluted made me wish evil things upon the architect of this mess.

2:15 there is nothing theoretical about it, its a fact. UVM turns a single step into four to fix a problem that didn't exist. The logic is that it is hard to maintain a single instance name in another class, so they created excessive dependencies for that class that require more instance names than before 3:00? Makes me rage. Because the analysis port doesn't use the factory, so you STILL HAVE TO MAINTAIN THE INSTANCE NAMES 16:10

livenoob

TLM Connections in UVM

TLM Connections in UVM

Introduction to TLM ports in uvm || UVM full course ||

UVM Simplified (#10 UVM Interface and Connections)

UVM: TLM Analysis Port Explanation with a Basic Example

UVM part5,TLM ports very detailed by dev

TLM (Transaction-Level Modelling) used in UVM (Universal Verification Methodology)

Transaction Level Modelling for OVM and UVM

How to Navigate Between Connected TLM Ports in the DVT IDE for VS Code

DVT Eclipse IDE Diagrams - How to Generate Diagrams Showing UVM Components and TLM Port Connections

UVM Connect

Introduction to Uvm tlm fifo ports || UVM full course || All about vlsi ||

chipverify uvm 11 UVM TLM

TLM(Transaction Level Modeling) w.r.p.t pyuvm and svuvm.

'Master UVM TLM Ports: Analysis Ports, Non-Blocking Get/Put, and TLM FIFO Ports Explained'

Analysis port and export/implementation port w.r.p.t SV-UVM

UVM tlm ports part 3 || UVM full course || All about vlsi ||

First Steps with UVM Part 3

Mastering UVM Sequencers: Connecting Drivers and Sequence Item Ports

UVM TLM PORTS PART 2 || UVM full course || All about vlsi

UVM Phases(Build_phase to Final_phase).

Easier UVM - Sequences

Local Constraint Modifer in SystemVerilog and UVM

How to Navigate Between Connected TLM Ports in the DVT Eclipse IDE

First Steps with UVM Part 1