⨘ } VLSI } 16 } Verilog, VHDL, Do You Write a Good RTL Code } LEPROFESSEUR

This lecture discusses important concepts for a good RTL design. The discussion is focused on blocking, non-blocking type of statements in verilog, multiple-drivers, assertions, fsm-deadlock, and in general good digital design practices. How can we verify using assertions finite state machine deadlock? What are key concepts we need to keep in mind when writing register transfer level code in verilog or vhdl, which can synthesis into quality digital circuits.

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[aradhanakumari]

Very nicely explained. Thank you so much for your efforts