ASPLOS'20 - Session 6B - Classifying Memory Access Patterns for Prefetching

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ASPLOS'20: The 25th International Conference on Architectural Support for Programming Languages and Operating Systems

Session 6B: Memory behavior — Where did I put it?

Title: Classifying Memory Access Patterns for Prefetching
Presented by: Grant Ayers (Stanford University)
Authors: Grant Ayers (Stanford University); Heiner Litz (UC Santa Cruz); Christos Kozyrakis (Stanford University); Parthasarathy Ranganathan (Google)
  1. ACM SIGARCH
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Комментарии
Автор

Exciting to see how optimizations in DataCenters which will eventually be used on all computation just as mainframes ideas were brought to the microchip.

KimoCrossman
Автор

Nice paper, the counterpart AsmDB for icache miss is nice as well, great job!

jiongwang
Автор

Great job and a very informative paper!
I know that this is not the most conventional channel for a question, but I guess I'll try anyway :)
Not all cache misses impose the same CPU penalty (cache miss cpu stall cycles) due to OOO etc. Since the timeliness considerations is essentially whether kernel execution time > cycles between cache misses to the same instruction, is it possible that the overall IPC (not including kernel) could be negatively affected if speculation and OOO can "hide" cache miss latency? (since only the DRAM latency is considered in the paper)
Thanks!!

shaibergman