Verilog Implementation Of 4:2 encoder Using Case Statement

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Verilog Implementation of 4:2 encoder Using Case Statement
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what if a comes in as any number from 4'b0000 to 4'b1111? 4'b1111 would technically be y=2'b00 as the first one is in the lowest bit of the number. For a=4'b1010 you should get y=2'b10 and so on. There are 16 possible values for (a) so your solution would fail for 12 cases wouldn't it?

ctbram
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Hi sir, how can we add/represent the Enable term here in the code?

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