2018 EuroLLVM Developers’ Meeting: M. Yatsina “LLVM Greedy Register Allocator – Improving ...”

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LLVM Greedy Register Allocator – Improving Region Split Decisions - Marina Yatsina, Intel

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LLVM Code Generation provides several alternative passes for performing register allocation. Most of the LLVM in-tree targets use the Greedy Register Allocator, which was introduced in 2011. An overview of this allocator was presented by Jakob Olesen at the LLVM Developers' Meeting of that year (*). This allocator relies on splitting live ranges of variables in order to cope with excessive co-existing registers. In this technique a live range is split into two or more smaller subranges, where each subrange can be assigned a different register or be spilled.

This talk revisits the Greedy Register Allocator available in current LLVM, focusing on its live range region splitting mechanism. We show how this mechanism chooses to split live ranges, examine a couple of cases exposing suboptimal split decisions, and present recent contributions along with their performance impact.
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