How to create your first VHDL program: Hello World!

In this video you will learn how to print text in VHDL. Creating a "Hello World" program is the most common way to start learning a new programming language.

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VHDL is a hardware description language, used for designing digital logic for FPGAs and ASICs. While this is true, VHDL is also just another programming language. A parallel programming language, or a concurrent programming language if you like.

When developing VHDL, you will most of the time be running your code in a VHDL simulator. And it is certainly possible to print text from VHDL inside of the simulator!

The bare minimum of a VHDL file includes an empty "entity" declaration. The entity of a VHDL file defines the inputs to and outputs from the module. While the entity is mandatory, it can also be empty. That's why we declare an empty entity in this video.

The "architecture" part of the VHDL file is where most of the code is written.

Inside of the architecture we can declare "processes". A process is a collection of code which is executed sequentially. VHDL is a parallel programming language, remember? But inside of each process, the code is executed line by line.

In this video we declared a single process.

Within our process we first typed in a line of code saying: 'report "Hello World!";'. This is one of the ways to output text in VHDL. This caused the text "Hello World!" to be printed to the console window in the ModelSim simulator.

Finally, after the Hello World line, we had to add a single line containing the text: "wait;". The reason for this is that it is a requirement in VHDL that every process contains some sort of Wait-statement. The single "wait;" caused the program to wait forever at this line.

When we run code in a VHDL simulator, like ModelSim, code runs in simulation-time. Real-time doesn't matter, because it's a simulation. All statements except for Wait-statements consume zero simulation time.

If we had not included any Wait-statements in our process, the program would loop indefinitely from start to end of our process. But the simulation time would always be zero, because Report-statements consume zero simulation time. The simulator would never be able to figure out what happens after the first initial timestep, and that wouldn't work. In fact, ModelSim would complain with the compilation error: "Process contains no WAIT statement".

[musicpartscollection]

I love how this tutorial is super duper easy to follow. Although a little slow for some people, it's great for dummies like me who need absolute every step in order to learn things.

[shovnikpaul]

Hi Jonas, I just wanted to say that this tutorial series has been incredibly helpful for me. I struggled a lot with VHDL initially despite having a lot of prior knowledge in programming and having taken 2 semesters of digital design. I love your style of presentation: very concise and systematic and helped me figure out what I was doing wrong in trying to learn the language. Thanks for all the effort!

[maramam]

I love your way of teaching, you show us errors and how to fix them

[DownTango]

very nice introduction to VHDL using ModelSim - that is what I needed :)

[thedorantor]

Thank you so much! I have zero experience with any sort of programming but I have to do this for college so I was at a loss until I found this

[antnew]

Just finished all 24 vids... this is a great little introductory course... I'm looking forward to the Fast-Track, should be fun.

[videosuperhighway]

lol I thought you were gonna build a 8bit CPU, send it to FPGA and then write an OS then C compiler to print hello world :)

[RAKESHYADAV]

very use for me .... especially error : "empty source files " occur my program .after watching your video
i solve the problem. thanks a lot, keep going on

[hinaasif]

please make VHDL
verification videos

[kSarah]

I should say that even if this is the first tutorial of vhdl, there is still a lot to explain before you get to tb and more. This is for someone who knows how the structure should look like and then it is time to practice!

[PTNLemay]

When I try to save the project, the options "Save" and "Save as" aways remain greyed out. Is there a way to save a project? Sometimes it will come back where I was if I close it and open it up again, but it gets really complicated if I'm running more than one project. Usually, because of this, I will have to create a new project whenever I open up ModelSim after having closed it.

[udakasarinda]

I am working in a project, in which I use FPGA for simulation acceleration. There I need some help with hdl coding for FPGA and Nios II processer

[diwakarm]

I am working on Smart fusion A2F500Mg484 board and libero soc v11.9 software. I have some doubts, will you help me out for that?

[HJahm]

The Problem with me " Error loading design" what is wrong 😢

[bolatdinc]

When I load this code into a real FPGA, How this FPGA sends "Hello World!" string to outside? I did not understand how this code work in real use case?

[kindjupiter]

Hello Sir, I did exactly the same steps as u explained but when I arrive to section start simulation, it comes the error message "cannot read stratup(-L):no such element in array" i couldn't fix it. If you know, would you please give a tip. Thank you

[khaldimohammedelhadi]

Hello,
When I do simulate it seems, error loading design. What is the What is the solution, please

[Ali-bgwt]

can I use vivado LAb edition for learning vhdl

[przemekbundy]

mozna latac samochodem. kto komu zabroni. mozna tez w vhdl pisac hello. skoro ktos uwaza ze to ma sens. to ok.