An Epyc Master Plan

Zen was only the beginning - but nobody expected this so fast.

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[RdTrpBrgr]

Me: I'll be late for work
Jim: Alright guys, how's it going
Me: ...Looks like traffic will be bad today

[ellsworth]

In case you may think he is blowing smoke up your butt. I worked in the semiconductor industry for 25 years and everything he said was correct. This is Intel’s Achilles heel. In order to get more intel cores you need a bigger die size. Bigger die sizes have lower yield. Don’t be surprised when Intel comes out with their version of infinity fabric. It is their only hope to compete in the future.

[adityac]

mind blowing analysis. I still believe in you prediction of an multi die graphics chip by AMD down the line as they have already mastered the process with ZEN. With a even matured infinity fabric I think the next most likely step is Graphics .

Love your long analysis videos, keep up the good work and quality of content.

[AlmightyGTR]

There is a reason I subscribed to this channel. It is not like the others who speak about products released and their respective benchmarks, but about the future to come. Good work brother!! Keep up the good job!! As an engineer who has studied ULSI design, I have to say that you have done a better job at explaining this than some of my teachers.

[TechEpiphany]

Thanks for allways delivering long, in detail but never boring knowledge

[themanwiththeplan]

thanks for linking the calculator man.

[brandonosborne]

Master Plan is what got me hooked on this channel. Great work then, great work now!

[Krazie-Ivan]

spot-on with yield concerns. i worked in an 8" fab (older - not even modern at the time) about 10yrs ago, & yield was everything. particles are your #1 enemy & reason for bad chips... the higher your number of processes (times a wafer travels through the different production steps around the cleanroom), the longer a wafer is exposed, & the lower your yield. actually clean "cleanrooms" are impossible, which made me instantly realize the brilliance of AMD's "gluing" several smaller chips together, while understanding why Intel server chips cost so much.

[andrew]

This is what a true tech journalist should be about. Straight facts and predictions based on real data. What the hell the rest of the tech press is doing? No one talks about these things. Imagine if tech channels with millions of subs made such quality content. The ones that can really shift masses opinion. When was the last time LTT and others that size made such videos? The tech press today seems to only care about gaming and RGB, nothing else. And as some say, nothing is more dangerous than an uninformed society. All of us being part of a capitalistic society, out most important votes are our purchasing choices.

[deadhell]

Possibly the best video so far!! Great work Jim as always!!

AMD has for a long time had to rely on multicore design, looks like Jim Keller was one of the best investments AMD have possibly ever made, which has enabled them to capitalize on their experience and strengths in this field.

[SgtStinger]

You forgot one very important thing here. AMD has said that they can use almost all of the defective chips, not only the good ones, due to Ryzen having less cache and PCIE than the full Zeppelin die. Thanks to the low core count models, AMD basically has a product they can put the chip in no matter where the defect is, no matter if it is in the cache, the cores, the PCIE controller or the Infinity fabric controllers.

[ZhangMaza]

Wow what a superb analysis, that is why i subscribed and bell your youtube channel Jim :)

[VigneshBalasubramaniam]

Man, I think you really nailed it this time. I would be interested to see if AMD can solve the latency issue of moving uncore components to a separate die, in addition to the latency disadvantage they have in cache whenever a request has to go over the Infinity Fabric. I am also interested in what AMD can do in GPUs, as I think AMD are making a lot of strides in GPU development, however, they are developments which don't serve games very well, as AMD are putting in features which game engines won't take advantage of for years to come, as game engines seem to be perpetually half a decade behind the hardware. In compute, AMD seems to be very competitive indeed, and they seemed to have focused on more general purpose half precision FP16 performance, rather than going the NVIDIA route and adding in essentially ASICs to be able to handle AI inference and training workloads (in their tensor cores). I think that decision may pay off in the end, as it allows them to handle a wider variety of workloads.

Once again, great video Jim, and great insight into the industry.

[amer-duqh]

*sees 1 notification on activity button, AdoredTV uploaded.*


YES!

[mOczakowski]

Funny how I was talking about this with my cousin just about a couple of months ago Jim :)
On one side AMD can put out twice the cores on the 7nm for servers/workstations/and high end gaming desktops @ around say twice the performance while offering even or better prices, but on the other end they can match performance and core counts while undercutting intel's price by about 50% and still make profit at it. It's a simple but brilliant design that basically has infinite scaleability.
Now if only they could do the same with their GPUs (vega chips) then they would do just fine in the market, and maybe even solve the insane gpu shortage at same time.

[m_sedziwoj]

Controler die don't have to be in 7nm process, it may be in 14nm, as Intel once show in past in they multidie chip

[nerdtechgasm]

Very well researched and presented Jim, all of your points are spot on (with one exception). Multi-die is required for the future nodes, this applies to everybody, not just AMD. I know for a fact that both Intel & NVIDIA are spending much R&D on novel multi-die architectures and fabrics, so AMD may only have a small lead time.

As for the exception, L3 cache takes up a lot of space, but it's quite resilient to defects, so binning chips with slightly less L3 is a way to improve yields. What they can't really do is separate the cache into another die and using IF to link it up, since L3 needs to be high bandwidth & low latency with multi-associations (direct interconnects) to all the cores in a complex. Cache over fabric, multi-hop from core <-> core would destroy performance. Not to mention increasing core counts per complex adds more traffic pressure to the IF links.

With their multi-die, AMD can aggressively launch on 7nm ahead of their competitors since they do it with volume and profit margins even on a low yield node that would restrict a monolithic chip.

[wahuwammedo]

i like how i get an intel commercial right before the video XD...

VERY informative btw. i don't know much about this aspect of chips and i'm still learning some basics in general, so for me this was EXTREMELY educational...

Plus i have some stock in AMD, so am very interested in their future prospects from the techies out there and this was BEAUTIFULLY done man!

Great video! Keep em coming!

[ujiltromm]

It's also important to remember that while Moore's law predicts an increase in transistor density, Dennard scaling predicts an increase in brown or dark silicon, i.e. transistor areas that must share switching time or remain in their state for extended periods of time, to maintain TDP constrains, leading to some parts of the chip that can't be activated while other parts are active, or reduced clock speeds (think AVX.)

Memory is essentially dark silicon, which makes increasing cache size an excellent candidate for die space to reduce cache misses, thus increasing IPS up to a point. Alongside it, specialized accelerated execution circuits are becoming more and more necessary to reduce the energy cost of execution through conventional computing paths (again, think AVX: reducing clock speed and being specialized to handle a specific type of load faster than conventional computing.)

Dark silicon and reduced clocks speed show there a limit to how many cores you can put on a chip before scaling plummets due to heat constrains, that is the essence of the Dennard scaling.

AMD has shown the way of breaking not only Moore's law, but also Dennard scaling with the Infinity Fabric and the multi-chip processor, allowing spreading the heat generation to keep it in check. It's only a matter of time before nVidia and Intel adopt an architecture akin to the Infinity Fabric.

[davidkennedy]

Wow, congratulations in explaining this to me in a way i actually understand. You don't realise what an achievement that is, I'm fairly computer dyslexic. Spot on mate!!!