Proteus VSM Simulation Transistor Logic OR Gate Labcenter Electronics #shorts

Proteus VSM Simulation Transistor Logic OR Gate Labcenter Electronics

This is a transistor logic simulation of an OR Logic Gate.

How to make this yourself in Proteus VSM
You will need to add the following components which were used ( pick them using the device picker ) :
Res, BC140 Transistor, Batt, Logicstate and Logicprobe

Complete the schematic as shown in the video.

Run the simulation. With the simulation running you can change the logic states and observe the OR Gate output on the Logic Probe output near the battery.

OR GATE TRUTH TABLE

A B Q
0 0 0
1 0 1
0 1 1
1 1 1

Transistor Q1 and Q2 act as the inputs. The collector of these two transistors ( which are connected together ) will be low when either/both inputs are high. Q3 acts like a NOT gate by inverting the level at collector of Q1 and Q2 to present the correct OR logic state at the output.

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[hasansaberi]

What's the voltage of the battery?