L-3.14: Gate 2014 Question on Set Associative Cache Mapping | Computer Organisation and Architecture

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This video contains Gate 2014 Question on Set Associative Cache Mapping.

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Sir, i think you have to cheak this video once again .My request to you sir making a correct video of this problem. This video can confuse to a new learner. big fan of you sir ..

sisirmondal
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I think address size should be 30 bit and block offset should be 3 bit.

muttarameshchandraprem
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How to identify whether a question is byte addressable or word addressable? In all the previous tutorials, you referred to memory in words(w0, w1, w2....) and calculated the offset accordingly. Now you are converting to bytes. In addition, it is mentioned that block size is 8 words, which means memory in block is counted in words. So, shouldn't it be word addressable instead?

harshavenkat
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yeah solved by myself on the basis of contents of last set associative video.... thank you so much sir.... awsm explaination

manjotkaur
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as the word is the minimum addressable memory unit, 3 bit needed to represent 8 words., with 5 bits we can represent 32 words .but we don't have 32 minimum addressable memory unit in single block.

sir please clarify

irshadahammed
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sir
block offset is 3 bits as 8 words in each block
and no lines in cache is 2^14/8= 2^11
and they will be 4 sets hence 2^9 lines


9 bits for set and 20 bit for tag.




Pls clarify how come the block offset id 5 bits

anilnarayana
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You can also solve this by converting physical address to only till kB and making it to cache as the cache memory is in kB.... Shortcut

himanshubarnwal
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🙏🤞✌👌
Can you please teach automata... Hardly request sir.. If possible... Want to be a good future lecturer like you🙏

easylearning.....
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Your lecture is awesome
Jay shree ram

adityasalvi
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block offset is to denote number of words in a block which is 8 so it should be 3 bits right?

gauravghosh
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abhi tk acha chal rha tha ...but yha confuse kr diya

shubhamSharma-unpy
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Sir Iss traha ke oor example kon c sitta pr millegi

gurdassindora
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U said no. Of lines divided by k - way associative, but u divided 2^9/2^2, where as it should be 9/4 ?!?!

Satya_vichar_
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i solved it wrong but got the right answer :D

rahularyan
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Hi sir,
In cache lines we are mapping the main memory blocks, for finding set number you have divided 16 KB with 32B, that means each line of size 32B. How can we get that sir?

csreenivasulu
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Total number of words in main memory = 4GB/4B = 2^30
Total no of words in Cache = 16 KB/ 4B = 2^12
Totol no of blocks in cache = 2^12/8 = 2^9
Total number of sets = 2^9/4 = 2^7

Total bits = 30
Set bits = 7
block offset bits = 3
Therefore, tag bits = 30-(7+3) = 20

prasasus
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sir, in previous lecture u told that it is word addresable, so if we take 5 bits for block offset then it will be byte addresable
why can we not consider physical address to be of 30 bits??
because there will be 2^27 memory blocks and each block will contain 8 words.
so we can take 27 bits for block no and 3 bits for block offset.
now the physical address is 30 bits and we can give 3 bits to block offset considering word addressable, 7 bits to set no.so for tag the bits will be 30-(7+3)=20
so 20 comes from this approach also,
which approach is correct considering byte addressable or word adressable??can u please clear this doubt

rahulanand
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Sir here word length is given 32 means 2^5 so each block should be 5*8 ?

raj
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Thanks so much, sir, the 'cache' is very clear now. :) can solve gate ques :) nicely explained each concept so well in the playlist.

tanushreemalviya
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U r grt sir....u hv made this very easy.... before I ignore COA bt coz of u ...I m used to vd this subject.... thnx alot sir 😍💞💞😘 u r a truly SMASHER😍

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