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Project Trellis: enabling open source tools for the Lattice ECP5 FPGA - David Shah - ORConf 2018
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Project Trellis documents the bitstream and low-level architecture of Lattice ECP5 FPGAs, which combined with the SymbiFlow tools enables a full open source flow from Verilog source to a bitstream. These FPGAs contain up to 85k logic cells and a range of features including DSPs, multi-gigabit transceivers and advanced IO functionality; unlocking applications such as networking, software-defined radio, high-resolution video, and testing processors powerful enough to run Linux!
The documentation includes core features including logic, RAM and IO tiles. Work continues on both more advanced features and developing a feature-complete open toolchain for the ECP5.
This presentation will discuss what approach was taken and what tools had been developed to create useful bitstream documentation within the constraints of publicly available interfaces; a reflection on what I think worked well and what could have been improved, and how to start you on your way to documenting more FPGA architectures for open source tools - it’s not as scary as you might think!
There will also be a live hardware demonstration of the SymbiFlow open source end-to-end flow for the ECP5.
Presenter: David Shah
David is an engineer at Symbiotic EDA, an open source EDA startup, and a MEng student at Imperial College London; he is passionate about open toolchains for FPGAs. His work on Project Trellis began after seeing the combination of the exciting new ECP5 boards being developed, and the need for larger FPGAs with open tools to enable a wider range of projects and break down misconceptions about the limits of open source.
Previously I have worked on projects including documenting the bitstream of the iCE40 UltraPlus FPGA and adding support to it to the icestorm toolchain.
Talk recorded at ORConf 2018, the Open Source Digital Design conference, held in Gdansk, Poland and organized by the FOSSi Foundation.
The documentation includes core features including logic, RAM and IO tiles. Work continues on both more advanced features and developing a feature-complete open toolchain for the ECP5.
This presentation will discuss what approach was taken and what tools had been developed to create useful bitstream documentation within the constraints of publicly available interfaces; a reflection on what I think worked well and what could have been improved, and how to start you on your way to documenting more FPGA architectures for open source tools - it’s not as scary as you might think!
There will also be a live hardware demonstration of the SymbiFlow open source end-to-end flow for the ECP5.
Presenter: David Shah
David is an engineer at Symbiotic EDA, an open source EDA startup, and a MEng student at Imperial College London; he is passionate about open toolchains for FPGAs. His work on Project Trellis began after seeing the combination of the exciting new ECP5 boards being developed, and the need for larger FPGAs with open tools to enable a wider range of projects and break down misconceptions about the limits of open source.
Previously I have worked on projects including documenting the bitstream of the iCE40 UltraPlus FPGA and adding support to it to the icestorm toolchain.
Talk recorded at ORConf 2018, the Open Source Digital Design conference, held in Gdansk, Poland and organized by the FOSSi Foundation.
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