Generating FPGA Implementation Metrics for an LTE HDL Toolbox Block - MATLAB and Simulink Tutorial

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The intellectual property (IP) blocks in LTE HDL Toolbox™ are designed to generate efficient FPGA and ASIC implementations from HDL Coder™. However, different devices have different architectures and characteristics so you may want to assess a block's performance on your device. Learn how to estimate implementation metrics, as well as how to run an FPGA implementation and examine the relevant metrics from its reports.

  1. MATLAB
  2. MATLAB
  3. Simulink
  4. MathWorks
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