180N. Latch dynamics, latched comparator

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Analog Circuit Design (New 2019)
Professor Ali Hajimiri
California Institute of Technology (Caltech)

© Copyright, Ali Hajimiri
  1. Ali Hajimiri (Academy)
  2. Latch
  3. negative resistance
  4. sense amplfier
  5. comparator
  6. latched comparator
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180N. Latch dynamics, latched comparator

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Комментарии
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11:31 Could you please explain the purpose of the PMOS latch? Why is it necessary to include it in the design?

אוריפקלק
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I understand the positive feedback.
But is not there a way that circuit output not saturate rather sattles to intermediate voltages?

ebadurrahmankhan
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12:20 it’s an attractive schematic style that drawing analog mosfets with arrows and digital mosfets with bubbles.

yasuhdie
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Hello. First. Thank you very much for the lesson.
Second. I have a question, I hope somebody could help me. When the current sources nmos transistors are clocked, the clock has digital levels? I mean, if the VGS is supplied by VDD, the VDS should be so high so they operate in saturation, or they could operate in lineal region?

Regards.

estebeer
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What is the use of Vref at the gate of tail current source ? Why Vref, why not any bias Voltage ?

jasdeepsingh
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Thanks for great lectures and I want to ask something. Can you re upload 9th lecture of circuit and system class. I am having difficulty to watch it. It is all green screen. Thanks again.

aliozdemir