5. Simulation Event Scheduling: SystemVerilog / Verilog - Simplified

In Verilog or SystemVerilog, the simulation process is divided into Time Slots, and each Time Slot is divided into event regions. This structure is called the simulation event scheduler.

Each event region includes Active, Inactive, and Non-Blocking Assignments (NBA) regions for design-related events and a Monitor region for system tasks.

The simulation can cycle through Active, Inactive, and Non-Blocking Assignments (NBA) regions multiple times in a Time Slot to respond to all scheduled events.

𝟭. 𝗔𝗰𝘁𝗶𝘃𝗲 𝗥𝗲𝗴𝗶𝗼𝗻:
- 𝗘𝘅𝗲𝗰𝘂𝘁𝗶𝗼𝗻 𝗼𝗳 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗲𝘀: Procedural blocks (initial and always) are executed.
- 𝗘𝘃𝗮𝗹𝘂𝗮𝘁𝗶𝗼𝗻 𝗼𝗳 𝗖𝗼𝗻𝘁𝗶𝗻𝘂𝗼𝘂𝘀 𝗔𝘀𝘀𝗶𝗴𝗻𝗺𝗲𝗻𝘁𝘀: The right-hand side of continuous assignments (assign) is evaluated and then the left-hand side is updated.
- 𝗕𝗹𝗼𝗰𝗸𝗶𝗻𝗴 𝗔𝘀𝘀𝗶𝗴𝗻𝗺𝗲𝗻𝘁𝘀: The right-hand side of blocking assignments (=) is evaluated and then the left-hand side is updated.
- 𝗘𝘃𝗮𝗹𝘂𝗮𝘁𝗶𝗼𝗻 𝗼𝗳 𝗡𝗼𝗻-𝗯𝗹𝗼𝗰𝗸𝗶𝗻𝗴 𝗔𝘀𝘀𝗶𝗴𝗻𝗺𝗲𝗻𝘁𝘀 (𝗥𝗛𝗦): Only the right-hand side (RHS) of non-blocking assignments is evaluated.

𝟮. 𝗜𝗻𝗮𝗰𝘁𝗶𝘃𝗲 𝗥𝗲𝗴𝗶𝗼𝗻:
- 𝗭𝗲𝗿𝗼 𝗗𝗲𝗹𝗮𝘆 𝗕𝗹𝗼𝗰𝗸𝗶𝗻𝗴 𝗔𝘀𝘀𝗶𝗴𝗻𝗺𝗲𝗻𝘁𝘀: Blocking assignments with a zero delay (#0) are executed.

𝟯. 𝗡𝗕𝗔 (𝗡𝗼𝗻-𝗕𝗹𝗼𝗰𝗸𝗶𝗻𝗴 𝗔𝘀𝘀𝗶𝗴𝗻𝗺𝗲𝗻𝘁 𝗨𝗽𝗱𝗮𝘁𝗲) 𝗥𝗲𝗴𝗶𝗼𝗻:
- 𝗨𝗽𝗱𝗮𝘁𝗶𝗻𝗴 𝗟𝗛𝗦 𝗼𝗳 𝗡𝗼𝗻-𝗯𝗹𝗼𝗰𝗸𝗶𝗻𝗴 𝗔𝘀𝘀𝗶𝗴𝗻𝗺𝗲𝗻𝘁𝘀: The left-hand side (LHS) of all non-blocking assignments is updated. This two-step evaluation and update process of NBA is for modeling the behavior of clock-to-Q characteristics of flip-flops.
- 𝗦𝗰𝗵𝗲𝗱𝘂𝗹𝗶𝗻𝗴 𝗡𝗲𝘄 𝗘𝘃𝗲𝗻𝘁𝘀: Updates in the NBA region can initiate additional events, potentially looping back to the Active region for the same time slot. This process is called a Delta Cycle.

𝟰. 𝗠𝗼𝗻𝗶𝘁𝗼𝗿 𝗥𝗲𝗴𝗶𝗼𝗻:
- 𝗦𝘆𝘀𝘁𝗲𝗺 𝗧𝗮𝘀𝗸𝘀: System tasks like $monitor and $strobe are executed. These tasks print the final values of signals at the end of the time slot.

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