Synchronous Counters Explained (Part-1)

In this video, the basic design procedure of Synchronous Counter is explained by taking the example of 3-bit Up and Down Counter.
Also, the general design procedure and logic circuit of n-bit synchronous binary counter has been discussed and the propagation delay of n-bit synchronous binary counter was calculated, and it was also compared with the propagation delay of n-bit ripple counter (Asynchronous Counter).

The following topics have been covered in the video:
0:00 What is Synchronous Counter
1:30 Design of 3-bit Synchronous Binary Up Counter using JK flip-flop
11:24 Procedure for designing n-bit Synchronous Binary Counter
14:25 Propagation Delay of Synchronous Binary Counter
18:34 Design of 3-bit Synchronous Binary Down Counter using JK flip-flop
24:22 Synchronous 3-bit Up/Down Counter

For more information, check the following videos related to Counters,
1) Introduction to Counter:

2) Asynchronous Counter:

3) BCD Ripple Counter:

This video will be helpful to all the students of science and engineering in understanding how to design a Synchronous Counter.

#allaboutelectronics
#digitalelectronics
#sequentialcircuits
#counters

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[sonyteetla]

Please clarify my doubt Sir, correct me if i am wrong .
Sir i think you gave wrong connection for CLK in up counting and down counting because in last video you gave table if it is negative triggering for up counter Q should connect as CLK to next flip and and for down counter Q(bar) should connect as CLK to next flip flop

For postive triggering up counter Q(bar) should connected as CLK and down counter Q should be connected as CLK to next flip flop

Here in this video you used postive triggering and gave according negative triggering connections

[AffanShaikh-fwhp]

In 3:38 when u were showing Excitation table of JK Fip Flop, the outtput Qn and Qn+1 is in the wrong sequence. Qn must be 0, 0, 2, 1 ehie Qn+1 must be 0, 1, 0, 1.??

[saraerikka]

Please what textbook would you recommend for practice questions on digital electronics

[alaapjagdale]

Sir, can we know which video editor or software you are using to make videos?

[shellsiz]

Can u help me i net to make synchrine counter from 9-0 only odd numbers for tomorow 13.6.2024

[adamsmuhammed]

How will the diagram look if we are to use NOR gate pls

[ducc]

sir in 12:12 shouldnt the F/F be negative edge triggered since the Q1 transitions taking place at falling edges(1-0) of Q0?

[MSDHZAHEEMI]

Sir, I think the way you calculated propagation delay is wrong.please check.because first AND gate and other ff s depends on first two ff