FPGA-based AES Cryptographic System [Block Diagram]

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[Digital / Embedded System] Designed, simulated, and implemented on FPGA an AES-based encryption/decryption co-processor:
• RTL coding: VHDL;
• Synthesis and device programming tool: Altera Quartus II Design Software;
• Logic simulation tools: Mentor Graphics ModelSim-Altera;
• FPGA development board: Altera Cyclone III FPGA Starter Board;
• Master processor programming language: Tcl-Tk.
  1. Mihai-Corneliu Cristescu
  2. FPGA
  3. AES
  4. Quartus
  5. Altera Cyclone
  6. ModelSim
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