Designing an Advanced Arithmetic Logic Unit for the PUTEY-1 Breadboard TTL CPU

After much effort, I have finally upgraded my PUTEY-1 breadboard TTL CPU to be able to do 64-bit math. This was done by significantly improving the Arithmetic Logic Unit over the original SAP-1 based ALU. In this video, I review the motivation and hardware design for this change.

Short video describing ATF22V10C Programable Logic Device chip:

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Chapters
00:00 - Intro
00:12 - Project Overview
02:09 - Multiplication Algorithm
09:15 - Design Goals
11:19 - Schematic Review - Overall
14:01 - Schematic Review - A Register
15:01 - Schematic Review - Temp Register
15:16 - Schematic Review - Logic Unit
16:35 - Schematic Review - Comparison Unit
18:23 - Schematic Review - Flags Register
20:00 - PLD Code for Flags Register
21:28 - PLD Code for Main ALU Logic
22:13 - Schematic Review - Control Logic
22:13 - Schematic Review - I & J Registers
24:00 - HL Register Zero Detection
24:20 - Other Schematic Changes
24:33 - Breadboard Layout Review
25:25 - Demonstration of 64-bit Math
26:11 - Investigate Errant LED Flashes
29:20 - Conclusion

[chevylization]

Just brilliant. I never had the guts to build something bigger than ten breadboards.
My tip of the hat Sr.

[HeadCodeMonkey]

I love this type of deep dive into your design, the trade-offs you have made and why.
I can't believe I hadn't considered using a PLD before, but that will really help me keep the size down when I get to my physical build.

Thank you for sharing such detail.

[IanWard]

Great video and very clearly explained!

[ChadwickVonLiechtenstein]

Wow, amazing video! I would really like to expand on the SAP-1 by Ben Eater and I am glued to your build. Great work!

[keithmn]

Great video, thanks. Wondering why you didn’t use a 74ls4078 or similar for the simple zero flag, rather than the 20 pin comparator chip with one side hardwired to ground.

[byronwatkins]

I would put a few Ohms in series with that LED anyway. If you do, then a small cap will filter out those blips.