Digital Design & Comp Arch - Lecture 6: Timing and Verification (Spring 2023)

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Lecture 6a: Hardware Description Languages and Verilog II
Lecture 6b: Timing and Verification
Date: March 10, 2023

02:06 Recap: Why Specialised Languages for Hardware?
05:18 Implementing Sequential Logic Using Verilog
07:47 The 'always' Block
14:37 D Flip-Flop with Asynchronous Reset
23:00 Sequential or Conditional
27:33 Non-Blocking and Blocking Assignments
32:59 Rules for Signal Assignment
35:08 FSM Example 1: Divide the Clock Frequency by 3
39:16 Implementation of FSM Example 1
43:42 Break
54:51 Lecture 6b: Timing and Verification
56:51 Tradeoffs in Circuit Design
57:57 Circuit Timing
58:36 Part 1: Combinational Circuit Timing
1:06:31 Example Worst Case tpd
1:12:34 Output Glitches
1:15:53 Optional: Avoiding Glitches Using K-Maps
1:20:33 Part 2: Sequential Circuit Timing
1:24:21 Ensuring Correct Sequential Operation
1:29:46 Hold Time Constraint
1:33:15 Example: Timing Analysis
1:36:42 Clock Skew

Recommended Reading:
====================
Intelligent Architectures for Intelligent Computing Systems

A Modern Primer on Processing in Memory

RowHammer: A Retrospective

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Computer Architecture Fall 2021 Lectures Playlist:

Computer Architecture Fall 2022 Lectures Playlist:

Digital Design and Computer Architecture Spring 2022 Livestream Lectures Playlist:

Digital Design and Computer Architecture Spring 2021 Livestream Lectures Playlist:

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Interview with Professor Onur Mutlu:

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Memory-Centric Computing Systems Tutorial at IEDM 2021:

Intelligent Architectures for Intelligent Machines Lecture:

Computer Architecture Fall 2020 Lectures Playlist:

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Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:

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02:06 Recap: Why Specialised Languages for Hardware?
05:18 Implementing Sequential Logic Using Verilog
07:47 The 'always' Block
14:37 D Flip-Flop with Asynchronous Reset
23:00 Sequential or Conditional
27:33 Non-Blocking and Blocking Assignments
32:59 Rules for Signal Assignment
35:08 FSM Example 1: Divide the Clock Frequency by 3
39:16 Implementation of FSM Example 1
43:42 Break
54:51 Lecture 6b: Timing and Verification
56:51 Tradeoffs in Circuit Design
57:57 Circuit Timing
58:36 Part 1: Combinational Circuit Timing
1:06:31 Example Worst Case tpd
1:12:34 Output Glitches
1:15:53 Optional: Avoiding Glitches Using K-Maps
1:20:33 Part 2: Sequential Circuit Timing
1:24:21 Ensuring Correct Sequential Operation
1:29:46 Hold Time Constraint
1:33:15 Example: Timing Analysis
1:36:42 Clock Skew

paulbird
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these lectures are incredible 😬 omw to create a GPU from scratch :P

allocator
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On slide 52, it says combinational delay should be minimum for hold time satisfaction. Shouldn't it be maximum.
On slide 69, tskew should be subtracted not added. Whether skew is postive or negative should be kept separate from the expression.

CyclopsOct