Cadence Virtuoso:: Design of NAND Gate Schematic || Part-1.

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This video is about the schematic design and simulation of cmos NAND gate using Cadence Virtuoso Tool.

Dr.HariPrasad Naik Bhattu

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Thank you so much sir for the detailed explanation with color visualization in the output...
☺

chayanaik

one of the excellent video which is very useful.Thnk u sir❤❤❤❤❤❤

helloworld-ms

Very good explanation sir, really u nailed it 👏👏

laxmik

Really very educational video. Thank you.

shrutikkapatel

How to post in linkedin sir after completing this nand tutorial, and what are the major points we are highlighted and it's(analog and digital both we are mentioned..?) on the linkedin platform I'm confused ..?? Could you tell me sir..? Some major highlighting points...!!

venkat

Thank you very much sir, can you upload the video to do simulation of netlist.v file using nclaunch which is generated in synthesis process.

pushparaj

Sir can you u please send me the specifications of this? I needed it for my mini project

DAEE_SANJEEVINIPoonaykarbk

hello sir did you can help how to design 3bit alu
with A*B, A+B, A-B and AxorB operation c1c0

kirubhakaranraman

How to make rise time and fall time are equal if the condition given in the LAB, NAND schematic

faizangokak

How to correctly build a 4-input NAND gate?🤔

zheniasg

Sir this simulation is which technology??

sangeetamugali

Check out full playlist link for Digital IC videos using cadence

vlsiforrookies

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