5-Stage Pipeline Processor Execution Example

Discusses how a set of instructions would execute through a classic MIPS-like 5-stage pipelined processor. Also looks at calculating the average CPI for the instruction sequence.
NOTE: This example assumes there is *NO* branch delay slot.

[richardhall]

I didn't know Tom Hanks made videos about instruction pipelining in his free time!

[Spinogrl]

Thank you so much! Youtube has taught me more about pipelines and data paths in an hour than my prof. has this whole month. They make it so much harder than it has to be!! Again, thank you!

[MrICH]

Still helping me in 2024 - big thanks!

[Vwcz]

Great video, and active in comments section. Excellent content creator! This is what we need. Thanks

[kevinle]

I am a bit confused as to how the iteration is from 5 to 18?

[boathecat]

For when neither branch taken, why does the last instruction "add $v0, $s0, S0" have no cycle?

[ahmadahm]

in case of forwarding beq schuld not wait for data cause it can get the data passed throw in the same cycle, unless you are assuming that EX stage for slt and ID stage for beq they are not happening in the same cycle:)

[selvalooks]

this is wonderful, pipeline fantastic explanation !!!!

[MrXinchuan]

I don't understand why you stall in the first beq (second instruction), but you don't stall lw (fourth instruction) and let forwarding take care of it. Because the previous instruction blt and add, both have the result ready after the execute stage

[Simppi]

This is a really great video, thanks! But I am still not sure on how data dependencies work. How do you know when a command has the data ready for another to use? For example, the BEQ command needs $t0 and it can get it after the SLT command has executed, but the next BEQ command has to wait for the LW command to get to the memory clock cycle. I would be very grateful for an answer, thanks in advance!

[_nognom]

The value for $t0 from the SLT instruction should be ready to forward at the later half of stage E, which is right before the early half of stage E for the BEQ instruction, which suggests that value for $t0 will be forwarded to the ALU instead of requiring a stall. Is this not correct?

[owenzhang]

If we dont have the last line, what the pipeline will be? Can we begin the IF of the first loop line directly in circle 14?

[wendyli]

Are we using forwarding in this problem? I'm confused on when the next instruction should start if we are using forwarding

[motorheadbanger]

There are a lot of things you are saying that contradict my teachings and readings on this matter. Can you please explain to me what you define as the following:

1) What is "branch taken/not taken"
2) What is forwarding

Additionally, are you saying that the resource in t0 cannot be accessed by the subsequent instruction until the memory stage of the previous instruction? And we have forwarding in this problem? Assuming yes, then your understanding of forwarding, and my understanding of forwarding contradict. Can you help explain?

[Manasrai]

Hey I just wanted to ask if an add instruction was dependent on a ld or lw instruction prior to it, would there be the same 2 cycle stall as there was for the beq instruction that was dependable on the lw instruction?

[mahanteshmise]

instruction no3 and no4 there must be stall at decode for instr 4.Correct me if i am wrong

[dontfckwithperos]

At first you say that Neither branch is taken but at the end the last one you tell us that again Neither of the branch is taken. I am confused can you help me understand if i get something wrong?

[albaraam]

I think in the third case you meant first branch (beq $t0, $0, end) is taken only

[yogeshbalbehra]

what are stages in typical four stage cpu pipeline? and whats the purpose of each stage? this question was in my exam. can you help me with answee

[jayz]

why is the iteration 14 is including the first W and does not include the last W (between 5 to17) ?