Demo of CDP180X - compatible CPU system on FPGA (coded using custom microcode compiler)

The core project here is the microcode compiler I created to simplify coding vintage CPUs, many of which were microcoded too. CDP1802 wasn't but it is an intriguing architecture so I wanted to try it out on something not typical. To validate the design end to end, I added ROM package containing monitor + Basic, RAM on the board and I am able to run Basic with frequency up to 25MHz.

The trace of CPU internal registers (going to UART/terminal and VGA is a routine in the CPU microcode, executed after each instruction fetch, but before instruction execution phase. This works at any speed (from 0 to 25MHz) but to allow "bit-banging" UART (on Q/nEF3) to work needs to be turned off.

For more info follow:


Hope you enjoy, feedback welcome!
Z.