14.2.2 SRAM

MIT 6.004 Computation Structures, Spring 2017
Instructor: Chris Terman

14.2.2 SRAM

License: Creative Commons BY-NC-SA

[girishgnair]

Is it possible to explain how to design a 6T sram cell to do both read and write operation ?

[ComputerScienceLessons]

Is it correct to say that when you want to write a new value into just ONE particular cell, you must first read ALL of the cells connected to the same word line (into the sense amplifiers), so that you can set the bit lines to the appropriate values, then effectively write everything back again?

[hiphopx]

So for the question posted during the write operation. Are the transistors designed that way to prevent the cell values from storing 1 on both sides?? also when i draw this operation out by hand and put 1 at each bitline, i see that the values of the cell do not change (because bitline GND overpowers cell Vdd and bitline Vdd doesnt overpower cell GND). But when i use 0 at both bitlines it appears to set both sides of the cell to 0. how does this respond when that cell is read and both appear to drop??

I theorize that the drops are similar throughout the read operation and the sensor amplifier doesnt pick up any change, so if thats the case would it be 0? is there actually another component involved for such cases? or am i completely lost?