Accelerating Development of DesignWare Mixed-Signal PHY IP with Custom Compiler | Synopsys

preview_player
Показать описание
Dino Toffolon, VP of Engineering for DesignWare IP at Synopsys, discusses his team's successful development of advanced, silicon-proven, mixed-signal interface IP using Custom Compiler. For more information, please visit:

  1. Synopsys
  2. Design
  3. Custom Design
  4. Analog Design
  5. Custom Design Platform
  6. Custom Compiler
Рекомендации по теме
Accelerating Development of 0:02:22

Accelerating Development of DesignWare Mixed-Signal PHY IP with Custom Compiler | Synopsys

Accelerating Development with 0:25:26

Accelerating Development with Organizational Opinions

Accelerating Development of 0:01:43

Accelerating Development of Complex Optical Systems

Accelerate Intelligent SLAM 0:06:03

Accelerate Intelligent SLAM with DesignWare ARC EV Processor IP | Synopsys

Improving Productivity and 0:01:10

Improving Productivity and Ease-of-use of COSIM Setup for Analog-Centric Users | Synopsys

Synopsys Demonstration of 0:02:40

Synopsys Demonstration of Android Neural Network Acceleration with EV6x

20nm Analog/Mixed-Signal IP: 0:31:59

20nm Analog/Mixed-Signal IP: Business As Usual?

Synopsys' New DesignWare 0:05:29

Synopsys' New DesignWare ARC HS Processors for Next-Generation Embedded Systems | Synopsys

DesignWare MIPI C-PHY/D-PHY 0:06:04

DesignWare MIPI C-PHY/D-PHY IP Performance at 24 Gbps | Synopsys

Silicon-Proven Automotive-Grade DesignWare 0:08:47

Silicon-Proven Automotive-Grade DesignWare IP

Design, Test & 0:58:20

Design, Test & Repair Methodology For FINFET-Based Memories Webinar | Synopsys

Rapid & Efficient 0:02:51

Rapid & Efficient Designs using ARChitect Configuration Tool for ARC Processors | Synopsys

DesignWare PHY IP 0:04:21

DesignWare PHY IP for PCI Express at 16GT/s and Beyond | Synopsys

Functional Timing Accuracy 0:06:48

Functional Timing Accuracy with ESP Device Model | Synopsys

Synopsys Custom Design 0:02:49

Synopsys Custom Design Family | Synopsys

Look Ma! No 0:42:14

Look Ma! No Hands! Test & Repair Requirements for Autonomous Vehicles | Synopsys

Enabling ​DNNs at 0:42:09

Enabling ​DNNs at the Extreme Edge: Co-optimize Circuits, Architectures & Algorithms | Synopsys...

Histogram of Gradients 0:01:36

Histogram of Gradients Demo on Synopsys DesignWare EV6x Vision Processor | Synopsys

DesignWare® STAR Hierarchical 0:05:05

DesignWare® STAR Hierarchical System | Synopsys

Available DesignWare MIPI 0:02:49

Available DesignWare MIPI D-PHY IP for 22-nm Process | Synopsys

Product Update: Broad 0:07:05

Product Update: Broad Portfolio of DesignWare IP for Mobile SoCs | Synopsys

Cadence solutions for 0:07:20

Cadence solutions for the latest PCIe 6.0 and 5.0 specifications

Product Update: Advances 0:03:46

Product Update: Advances in DesignWare Die-to-Die PHY IP | Synopsys

Synopsys Demonstration of 0:02:01

Synopsys Demonstration of Deep Learning with VGG16 on the DesignWare EV6x Vision Processor