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The Magic of RISC-V Vector Processing
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The 1.0 RISC-V Vector Specification is now Ratified, and the first pieces of silicon using the new spec are starting to hit the shelves. I go over the utility of Vector Instructions, why you would want them, why you should care, and how to use them in raw assembly code! We also touch on some complex computer engineering topics like Vector Length Agnosticism.
By the end of this video, you'll understand why this is such an exciting time in computing history!
Note: This video is *not* sponsored, I just think the K230 is an interesting chip.
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RISC-V Official 1.0 Vector Spec:
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Follow LaurieWired on Social Media:
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Timestamps:
0:00 RISC-V ISA Overview
1:50 What are Vector Instructions?
5:46 0.7 Draft Spec vs 1.0 Ratified Spec
7:13 SoC Overview
8:15 Vector Assembly Code
11:01 Real Time Demonstration + GDB
13:20 FFmpeg RISC-V Vector Patch
14:51 Closing Thoughts
By the end of this video, you'll understand why this is such an exciting time in computing history!
Note: This video is *not* sponsored, I just think the K230 is an interesting chip.
---
RISC-V Official 1.0 Vector Spec:
---
Follow LaurieWired on Social Media:
---
Timestamps:
0:00 RISC-V ISA Overview
1:50 What are Vector Instructions?
5:46 0.7 Draft Spec vs 1.0 Ratified Spec
7:13 SoC Overview
8:15 Vector Assembly Code
11:01 Real Time Demonstration + GDB
13:20 FFmpeg RISC-V Vector Patch
14:51 Closing Thoughts
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