L27-B SRAM: Sense Amplifier, Row and Column Decoder, SRAM Timing, Layout

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SRAM: Sense Amplifier, Address Decoder, Row and Column Decoder, Timing and Layout

Figures without citations: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies, A. Pavlov and M. Sachdev, Springer, 2008.

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At 23:55 I don't get why BL gets now pulled to 0 if we want to write a 1. I get that the first Write Driver Circuit is working and here we pull BLB to 0 to write a 1 at BL. But the other two circuits don't make sense, as they do the opposite. I now seen many of these write driver circuits in books. Can you please explain, why the first circuit pulls BLB to 0, while the others pull BL to 0, even though all circuits want to write a 1 ?

maxmuller

hello, my question is where the gate voltage for EQ comes from in the sense amplifier is that connected to your sense enable line or?

Anacortesboyz

Use different symbols for PFET and NFET or it can be confusing or misleading!

owen

L27-B SRAM: Sense Amplifier, Row and Column Decoder, SRAM Timing, Layout

L27-B SRAM: Sense Amplifier, Row and Column Decoder, SRAM Timing, Layout

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