SDC 2017 An NVMe-based Offload Engine for Storage Acceleration - Stephen Bates and Sean Gibb

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Abstract:
FPGA-based storage acceleration promises the capability to offload the host CPU for processing intensive tasks such as error correction and deduplication. By leveraging the NVMe host controller interface specification to provide access to storage acceleration functions, existing drivers and storage tools can be used to test, benchmark, and deploy the accelerator card. We describe the design and testing challenges of implementing an NVMe host controller interface for acceleration on a RISC-V microprocessor for an FPGA acceleration platform. The architecture of the RISC-V implementation of the NVMe controller is described, including the RISC-V processor and tool flow, with an emphasis on describing the design tradeoffs required to achieve the desired performance. We discuss the advantages of advanced NVMe features, including Controller Memory Buffer (CMB), for use in remote acceleration using NVMe Over Fabrics.