FSK Modulation and Demodulation

An explanation about FSK Modulation and Demodulation.
In this video, Gregory explains the full topology of an FSK demodulator, showing how the bitstream is recovered, how time is synchronized and frequencies offset are compensated.

FSK modulation encodes the data in shifts of frequency. In the case of binary signaling, two different frequencies are used, representing 0 and 1.

The process of demodulation is done using two NCOs - Numeric Controlled Oscillators - and average filters, actually implementing a sample-by-sample DFT in real-time.

The energies at the two different frequencies are compared to determine if the data bit is a 1 or a 0.

The continuous recovered bitstream is sampled with a NCO running at the baudrate and a Gardner Time Error Detector in conjunction with a PI controller corrects the sampling interval/point.

Frequency offset are compensated using a slow time-constant servo-loop that equalize average energy of the sampled points.

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A related video about Clock Recovery PLL:

Learn how a Costas Loop demodulator works for PSK modulations:

Article about how DFT works:

00:18 - Introduction
03:36 - Overall demodulator topology
06:15 - Detecting energy without filter (DFT)
10:38 - Quadrature detection topology
13:24 - Time Recovery/Synchronization
16:55 - Offset compensation/Carrier Recovery

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[danielsolis]

Super great video as always, lot of learning.
Just seeing this topic at school, maybe Ill try to implement it for the lab

[SandeepKumar-jjzi]

Nice, So PSK too has spectral leakage like discrete FSK ?

[MR-fspc]

Awesome video, once again a pretty complex subject presented in a clear and engaging way. Makes me want to try and build one 😉

[jakubniemczuk]

That was a pretty solid and straight forward presentation. Great work!

[PetakyahBuckley-htiz]

@2:18 for cpfsk how do you make two constants to manipulate the single oscillator. Is each constant a different frequency? What are the constant designs? I’m aware the switch is the binary encoder. And wouldn’t the oscillator be considered a code itself, like wouldn’t it be a zero and wouldn’t the two constants both be a 1. Idk I got lost when I didn’t know the value or design of the F1 and F2 constants

[johnaweiss]

Doesn't the time-sync circuit add latency? It adds parts and complexity. Instead, couldn't the xmtr send a clock-sync code at the beginning of each packet, and eliminate the whole Gardner/PIC?

[johnaweiss]

How can there be frequency offset or drift if xmt and rcv are identical transceivers running identical crystals?

[johnaweiss]

4:36 Is the energy detector circuit typically the same circuit as an RSS detector? Or will it operate at a different voltage scale or input impedance than an RSS detector?

[mhmtsrml]

What is the program, please.. How can i do it?

[aayush_deo_ranchi]

can the integrator be made from 555 timer

[shamilniftaliyev]

Very good content, keep it up! (but I should admit your English accent is like a torture)

[danielvogel]

who's watching this genius in 2024? thanks Greg, you are the best!!

[phillipneal]

Wow ! I gotta think about this. I only need an fpga to make an fsk receiver !!! Even a 4fsk receiver like for WSPR ?

[cjlvossen]

Would be nice to do a follow up on a real FPGA implemention. Great contant!

[skepticengineer]

great presentation! i wonder, is the explained method the principal of how a PLL works? or a freq discriminator?

[bitsnbytes]

Wow, that was a truly excellent presentation (love your enthusiasm !). I hadn't thought about the clipping trick (near 20:25).
As I understand it, it essentially means that we only need to consider the higher order bit of each input sample, right ? (I'm thinking saturated 8-bit signed values, so either +127 or -128).
Because assuming that it is the case, since quadrature demodulators essentially multiply the input signal by a couple of out-of-phase reference signals (sin & cos), maybe we can make these reference signals square as well. So we'd only need 1-bit multiplications, which is essentially what a XOR does (binary input signal XOR higher order bit of two pairs of counters running at F1 and F2, each one shifted by 90° with respect to the other).
It's super late here, and I'll have to give it more thought tomorrow but... I can see a bunch of neat optimization opportunities here, both for FPGA and CPU implementations.
In any case, you earned my subscribe :-)

[y_x]

What a complicated way to decode FSK. It was invented in the 1930... when no computer existed. The analog circuit used to decode FSK is very simple!

[ahmedgaafar]

Gregory ..you are really a talented teacher...i have read a lot of books in communications and saw hundreds of videos from the Gurus ...and yet you are the best without any doubt....just a little note, , , , FSK sync can also be done by a matched filter that synchronizes with a chirp signal that preludes the message data stream, of course the chirp must be added during the transmission....but hey this video is no different than your other excellent videos...well done...and in your words... it is really beautiful.

[kapilrthr]

Sir, you are a saviour..a big thanks from India👍👍