Lecture 20: Address Sequencing in Microprogrammed Control Unit

#NextAddressCalculation #AddressSequencer
Address Sequencing:
An initial address is loaded into the control address register when power is turned on in the computer. This address is usually the address of the first microinstruction that activates the instruction fetch routine. The fetch routine may be sequenced by incrementing the control address register through the rest of its microinstructions. At the end of the fetch routine, the instruction is in the instruction register of the computer.
The control memory next must go through the routine that determines the effective address of the operand. A machine instruction may have bits that specify various addressing modes, such as indirect address and index registers. The effective address computation routine in control memory can be reached through a branch microinstruction, which is conditioned on the status of the mode bits of the instruction. When the effective address computation routine is completed, the address of the operand is available in the memory address register.
The next step is to generate the microoperations that execute the instruction fetched from memory. The microoperation steps to be generated in processor register depend on the operation code part of the instruction. Each instruction has its own microprogram routine stored in a given location of control memory. The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process. A mapping procedure is a rule that transforms the instruction code into a control memory address. Once the required routine is reached, the microinstructions that execute the instruction may be sequenced by incrementing the control address register, but sometimes the sequence of microoperations will depend on values of certain status bits in processor registers. Micro programs that employ subroutines will require an external register for storing the return address. Return addresses cannot be stored in ROM because the unit has no writing capability.
When the execution of the instruction is completed, control must return to the fetch routine. This is accomplished by executing an unconditional branch microinstruction to the first address of the fetch routine. In summary, the address sequencing capabilities required in control memory are:
1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.

[keylife]

Nice Effort and clear explanation bro. Hope to see new useful videos soon.

[gamingmachine]

sir naya video haru halnu paryo atinai helpful vaira cha tapaiko video haru

[snr]

Sir ajai video haru halna paryo
This was really really helpful upto this point.!

[pratikthapa]

please upload other videos of this subject too. its been so helpful till now.

[kripapokharel]

Very nice videos dai ajhai upload garnu paryo

[tikaramdahal]

Thank you bro.... Aba conditional branching and mapping bujnu theo... :P :)

[TechDaju]

Much helpful sir..Aaru videos ni chaiyo plz..

[peaceenlightenment]

Daju
EMBEDDED SYSTEM PROGRAMMING ko video chaieyo BIT ko lagi