VLSI ARCHITECTURE OF SET PARTITIONING IN HIERARCHICAL TREES

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DESIGN DETAILS
This design is based high-throughput memory-efficient architecture for the set partitioning in hierarchical trees (SPIHT) image. To verify the algorithm, we used Verilog HDL with Matlab program. The simulation is carried out using Matlab along with Modelsim software where the input image converted into corresponding pixel values using Matlab then those values are processed using SPIHT algorithm in Verilog HDL.

REFERENCES
Reference Paper-1: VLSI Architecture of Arithmetic Coder Used in SPIHT
Author’s Name: Kai Liu, Evgeniy Belyaev, and Jie Guo
Source: IEEE
Year: 2012

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