Logic System Design | Module 4 Part 1 | CST203/ECT203 | KTU S3 CS/EC | Logic Circuit Design

#ktu #lsd #module4
CST203 :- Module 4 Syllabus:

Sequential logic circuits:
Flip-flops- SR, JK, T and D. Triggering of flip-flops- Master slave flip- flops, Edge- triggered
flip- flops. Excitation table and characteristic equation. Registers- register with parallel load.
Counter design: Asynchronous counters- Binary and BCD counters, timing sequences and state
diagrams. Synchronous counters- Binary Up- down counter, BCD counter.

ECT203 :- Module 4 Syllabus

Building blocks like S-R, JK and Master-Slave JK FF, Edge triggered FF, Conversion of
Flipflops, Excitation table and characteristic equation. Implementation with verilog codes.
Ripple and Synchronous counters and implementation in verilog, Shift registers-SIPO, SISO,
PISO, PIPO. Shift Registers with parallel Load/Shift, Ring counter and Johnsons counter.
Asynchronous and Synchronous counter design, Mod N counter. Modeling and simulation of
flipflops and counters in verilog.