FFT development on an FPGA - Simulation Design Flow using Quartus and Verilog (no board required).

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This video shows how to design an FFT in Quartus and simulate it using Modelsim. A Numerically Controlled Oscillator (NCO) is used as the input signal to the FFT. Testbench code is listed below (the FFT wrapper code is in the previous video description.)

`timescale 10ns/100ps
module testbench;

reg clk;

wire [13:0] fsin_o,fcos_o;
wire [24:0] real_power_sig, imag_power_sig;

initial
begin
clk = 0;
end

always
begin
#10 clk = !clk;
end

wire reset_n;

nco nco_inst(
.phi_inc_i (32'd41943040), // .phi_inc_i
.fcos_o (fcos_o), // .fcos_o
.out_valid (out_valid) // .out_valid
);

fft_wrapper fft_wrapper_inst
(
.clk(clk) , // input clk_sig
.in_signal(fsin_o) , // input [13:0] in_signal_sig
.real_power(real_power_sig) , // output [24:0] real_power_sig
.imag_power(imag_power_sig) , // output [24:0] imag_power_sig
.fft_source_sop(fft_source_sop_sig) , // output fft_source_sop_sig
.sink_sop(sink_sop_sig) , // output sink_sop_sig
.sink_eop(sink_eop_sig) , // output sink_eop_sig
.sink_valid(sink_valid_sig) , // output sink_valid_sig
.reset_n(reset_n) // output reset_n_sig
);

endmodule

Visual Electric

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Hello sir, many thanks for your video, it really saved my life, but I may raise a simple question, it seems that the control_for_fft module only processes real signals rather than complex signals, as I saw that outimag of control_for_fft was assigned as 16'd0. What if the input signal is a complex signal, and the complex signal is merely a one-line 16-bit data? In other words, what if the 'insignal' of control_for_fft is a 16-bit complex signal? What are the possible changes of the module control_for_fft, if that is the case? Looking forward to hearing from you, thanks!

_Tobias_

Hi, , great videos.
I did the exactly same step as your tutorial here. But the output is different. I cant get the spike, my output signal, source imag always zero, and source real is still sinusoid, like invers of the input sink real. Can you help me, whats wrong? Thank you

rryouluvv

Do you familiar with Cyclone V SoC board?, Im planing to build an simple SDR on this board, I already have the AD-DA daughter card and I intend to transfer the I-Q data to the computer using ethernet transmittion. It will be awsome if you can share some experiences with the SoC and how to work on it!

hightlightlol

the font is too small to view it on a laptop or phone. I think a smaller resolution, or higher magnify ratio is better.

fish-utf

Is programming altera cyclone ii different from cyclone iii?

thabangntema

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