Testability of VLSI Lecture 4: Logic Simulation

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Simulation for Design Verification, True Value Simulation, Logic verification of a 32-bit ripple-carry adder, Fault simulation for test generation, Modeling Circuits for Simulation, Function or 1. Behavior Level, 2. Logic Level, 3. Switch Level, 4. Circuit Level, 5. Timing Level. Why Circuit Level Modeling Is Important, Modeling Gates for Z and X inputs, Modeling XOR/NOR Gate, Limitation in Simulation, Design for Testing, Modeling Circuits for Simulation, 1. Zero Delay Model, 2. Unit Delay Model, 3. Multiple Delay Model
Tr and Tf different for each type of gate. 4. Min. Max Delay, Algorithms for True-Value Simulation, Circuit Simplification, Circuit Levelization, Compiled-code simulations, Event-driven Simulation, Zero delay, Nominal delay.
  1. Sanjay Vidhyadharan
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