#22 Part 2: UART-RxD Serial Communication using an FPGA Board ➟ Step-by-Step Instructions

Building a UART communication between the Basys 3 board and the computer terminal. When the key strobe on the keyboard (from the computer) is pressed, the 8 bits will transmit from the keyboard to FPGA through USB-UART port on Basys 3 Board. 8 LEDs [7:0] on Basys3 will be used to show the binary value of the ASCII character. All receiving is triggered when a key is pressed on the keyboard. There is a button to reset the output led as well.

Table of Content
00:15 Introduction to the Project and Pre-Requisite
00:50 DEMO | Preview
01:35 Background and Theory | Functional Block Diagram
12:50 Verilog Coding
28:00 Synthesis & implementation
29:40 Generate & Download Bitsream file on to the FPGA Board
30:35 Connecting Window Terminal
31:15 Check the functionality

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Credit: 👍
- Sound 🎵 : Camtesia
- Sound 🎵 : MelodyLoops

#electronicswithprofmughal #UART #UARTcommunication #Receiver #FPGA

[ilanmer]

Just posting for anyone who was confused as me, about how prof. Mugahal samples once at the middle (after 2 sample ticks) and then at regular intervals (at 4 sample ticks)..
So in the first always block he makes the baud generator, that allows to to receive the data only every tick of data bit. So even though the "shift" is always on(line 97), it only allows to receive the data(line 64) every data tick (which is equal to 4 sample ticks)(61).

So here's the big picture, the first time data comes in we go to state 1 and activate "shift" after half the ticks, which we want. but then this line(97) doesn't mean anything because shift is already constantly 1, so now we skip to next line(98) automatically. and this next line ensures we sample every 4 ticks. Very nice coding.
Thank you for coming to me TED lecture, hope I was clear:)

[oscartf]

This video really helps me to implement UART in my project. Thank you very much

[venti]

you have just saved my life. Respect from China

[ilanmer]

Hello sir, Thank you as always. I have a question regarding your code;

Don't we set "inc_samplecounter" to a logic 0(line 79) and to a logic 1(line 104) at the same clock cycle sometimes? happens with other regs as well.

because we first set it to zero every fpga clock rise but then is set it to one if we are at state 1.

Thank you very much!

[arnulfohernandez]

Hello, great explanation and implementation, it could be implemented to receive two bytes.

[subashiniparamanandan]

Thank you so much for the video. Looking forward for more videos on FPGA.Can you provide the access to the code.

[maximuslegend]

Hii professor
I needed a help on interfacing physical keyboard with the basys 3
I want to use the keys of the keyboard as an input device for the basys 3 just like the 5 buttons present on it
Is it possible to use keyboard as an input device for various programs?

[omerfaruksahin]

Thank you for the video can you give access for the code

[belarbinaouel]

Hi, do you have anya idea how to usb 3300 ulpi with fpga to impliment a usb host?

[dheerajchumble]

Can you please make a video on 16x2 LCD interfacing with FPGA.

[swangp]

Hi, this is a great video. I have an idea to instead of pressing a key on Teraterm, I can flip 8 bits of data from my board, press an onboard button to transmit, and then have it output the corresponding 8bit data as a letter on the terminal. Any tips to go about this? Thanks and keep up the great work!

[khevanapurohit]

I had a doubt that are we using the another basys 3 board for this receiver part? Or we can do the tx and rx using same board?

[emirhansorgun]

RxD input in the constraint file should be like this:

##USB-RS232 Interface
set_property PACKAGE_PIN B18 [get_ports RxD]
set_property IOSTANDARD LVCMOS33 [get_ports RxD]

[pragatimali]

If I change the div_sample I'm not getting the same output. On 4 only I'm getting desired output. What is the reason for that

[AhmedAli-rwwt]

Sir, I am confused on division sample that why is it chosen to be 4? Why not any other number?

[Kasten_]

I need the full constraints because my fpga receive the signals but don´t show in the leds, can somebody help me?

[janglipilla]

Sir still i am confused why we multiply BaudRate by 4

[callistuspanigeorge]

Thank you so much. With your help I have successfully implemented uart receive on my spartan 6 fpga. Can you please help me how to recieve multiple bytes of unknown length and a control signals goes high when all bytes are received?

[raybernal]

very well explained can you give me acces to files?

[ashishanand]

prof. mughal can you let the access to project files, it shows access denied