Behavioral Modeling Style Intro #ModelSim #Verilog

Behavioural modelling is the highest of level abstraction that completely depends on the circuit behaviour or on the truth table.

If you know how your circuit will behave, you can design it. In fact, you can design the module without knowing the components of the hardware.

However, even though it is the closest in terms of natural language understanding of the circuit functionality, this modelling type is hardest to implement and synthesize. Hence, it is utilized for complex circuits such as pure combinational or sequential circuits.

A module developed using behavioural modelling contains initial or always statements, which are executed concurrently (according to the parallelism of the model). The procedural statements in the module are executed sequentially.

At time=0, both the initial and always will execute and then, always statements run for the remaining time. Here’s the syntax:

always [timing control] procedural_statements;

initial [ timing control] procedural_statements;