VHDL project :Digital Pass Filter Simulation (low pass,high pass, band pass, band reject).flv

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Hello friends...
This is the digital pass filter simulation project, The system having two clock frequencies as a input, one for the reference clk to generate time period of 1 sec and another is the input measuring frequency coming from any other hardware or receiver. the system can works upto the 200 MHz frequency and two frequency points these are 50 MHz and 100 MHz.
When the input frequency is lower then 50MHz then system transfer the input clk to low_pass output, if the i/p frequency is higher then 100MHz then i/p clock will move to high pass output, if the frequency is in the range of 50 to 100MHz then the input clock will pass to band_pass and if not in the range of 50 to 100MHz then move to band reject output.
This project is based on simulation, and you can further work to develop this simulation system on hardware as well...
You can choose this project as a minor project or major project as well in your college.
I hope you like this video, Thank you for watching.

Friends, I would love to read your suggestions and comments so please share your views.
  1. HDL Design Lab
  2. vhdl
  3. verilog hdl
  4. hdl
  5. simulation
  6. vlsi
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Комментарии
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i am working on adaptive notch filter and really need to it.

hemkumarpatel
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The code is not clear, where is the PROCESS ?

elisagranata
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i like your video but not all of your source code is visible

mebratwgewergs
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dear sir
send me this code please.
good bye

jafar