OCR A-Level Computer Science: CPU Performance in 5 Minutes - H446 Revision

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The Fetch-Decode-Execute Cycle is a cornerstone in understanding how CPUs process instructions. In this 5-minute breakdown tailored for OCR A-Level Computer Science students, we'll demystify the FDE Cycle, ensuring you're well-prepared for the H446 exam. Be sure to subscribe for more pinpointed 5-minute topic summaries!
  1. Tech Head Online
  2. OCR A-Level
  3. Computer Science
  4. H446
  5. 5-Min Revision
  6. FDE Cycle
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think you have got this the wrong way round. 
CISC machine instructions are actually more complex than RISC ones - they do more. This means programs in CISC use less instructions than RISC ones - more complex hardware means less complex software. For example a CISC chip might have a single command to multiply 2 numbers where in a risc equivalent the multiply might me broken into several simpler commands. CISC design philosophy dates back to when RAM was extremely expensive so as each new generation of CPU was released they would build in more and more complexity into the hardware so that programs would need less instructions.

djneils