Stop Watch design project implementation using FPGA

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A Stop Watch which has features like STOP/START, LAP/SPLIT, CLEAR, RESET, STUDENT ID display, LED Status, etc. The specification of the stop watch is shown in the video and the implementation is demonstrated in the video.

The design is implemented in VHDL and the FPGA board used is DE1 Nano board from Terasic which has a Cyclone V FPGA (Field Programmable Gate Array). The design can be implemented on any FPGA board (for e.g., DE0 Nano board from Terasic) since I can provide the source code and the other necessary guidance.

This can be used as a project for Engineering Students or as a prototype to demonstrate the Stop Watch product.
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Hi Sarath.. Can u plz send me the source code..? I'm a student.. It's for my assignment purpose..

musicbeat
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can you please provide me with the source code for university study purpose?

elomariamin
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