Read, write and modify control and status registers in RISC-V

This video discusses about how to read, write and modify control and status registers in RISC-V.

[LearnRISCV]

Correction: At 7:07 the immediate variant for csrrw misses a suffix "i". It should be csrrwi rd, <csr>, uimm[4:0]

[NasirKhanPAK]

Super good thanks for the lectures series please make it a compressive lectures series about RISC-V. and yes one request to you kindly order the videos by numbers or whatever suits you so we watch it in a systemic way to learn more about RISC-V. thanks for the lectures its super good. thanks a lot.

[mekatronikmuhendisi]

How can I configure this? Are there any videos? I'm new to this, I designed a processor. I need to debug. But tools without an interface, such as Spike, are very troublesome. Program vehicles like RARS do not have all the systems.

[abdulwadood]

What is this toolchain that you are using to compile c program into RISC-V