How to get BCD from Binary with verilog and the Double Dabble algorithm!

**NOTE: the final Verilog script in this video is intended for 4 digit conversion where the initial example is for 3 digit conversion.**
In this video we go through the algorithm to create BCD (Binary Coded Decimal) from Binary with the double dabble method. We then show a verilog example of how to code the Double Dabble algorithm! BCD is a very important number coding in order to drive things like 7 segment LED displays and more. This code will eventually be uploaded to an FPGA board to drive a set of 7 segment displays. The code can be downloaded from my GitHub link below. Please keep an eye out in the description for the upcoming videos that tie into this project! Have a great day and don't forget to #LoveWell!!

GitHub Code:

Binary to BCD Simulation video:

BCD to 7 segment decode:

[S_P_S]

Hi . Nice explanation . But I have one doubt . In order to get number of nibbles we did ( 2 ^ (No. of bits required to represent Number) ) . Here we have considered 8 bits but observing it carefully, 5 bits are enough . Then Why did we occupy extra bit positions ?

[glennicholls]

Where is your test for this? I see you have a simulation, but how can you trust your code if there are no test cases?

[serj]

Great example! A very old Xilinx application note, XAPP029 also covers this.

[crohrer]

Your example used 20 bits, but your code used 28. I believe your code is intended for a 12 bit input instead of an 8. Confused me for a moment. Also, I don't believe your code is going to work the way you described. You've got multiple assignments to the partial result.

[nikitaafanasyev]

guess it is incorrect code. You need to add 3 for every nibble exceeding 4 every clock, but your code only allows update single biggest nibble which happens to be >4.