Binary coded decimal (BCD) counter with parallel loading implementation on FPGA

Excited about getting started with FPGAs!! Well, you are at the right place.
Join us as we demonstrate how to implement a BCD counter with parallel loading on a Xilinx Spartan 6 FPGA.

Counters are very important for any digital systems as it helps us to get different signals from a system clock. Decimal numbers are easy for humans to visualize and that's why we are implementing a counter that counts from 0 to 9 and then goes back to 0. An additional feature in this counter is that parallel data can be loaded which is of great use. These counters can help in keeping track of the functions inside digital systems.

Find out how easy it is to go from logic to practical implementation on an FPGA development board. We use the Xilinx ISE suite to demonstrate how to use Verilog to code our RTL design and translate it onto the EDGE Spartan 6 Development board

This video has been submitted by KRSSG, IIT Kharagpur under the Robocraze Club Outreach Program. Video credits: Anubhav Prasad