GPIO Output Configuration | Open Drain configuration | Push Pull configuration

Fundamentals29 GPIO Output Configuration or Open Drain configuration or Push-Pull configuration

Friends welcome to this video series on Embedded System. GPIO which stands for general purpose input output is one of the first things to play with while learning Embedded System programming.
So in this video, let's continue our discussion on this topic and try to understand what is the need of Pullup and pull down registers while making use of GPIOand some of the most commonly used GPIO output configurations like Push pull and Open Drain.

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#OpenDrainConfiguraion
#PushPullConfiguraion
#HowToTurnOnLed
#PullUpResistor
#PullDownResistor

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[vickysom]

explained in very nice and calm manner. thank you

[macimaci]

Thank you from Germany. Very good explanation.

[jatag]

Excellent video, your diagrams are so clear. Very helpful for me!

[ticky]

Thank you for sharing! Your video is so concise and neat!

[ilseguerra]

excellent explanation :) Could the open drain be used to generate a PWM with a higher voltage than the one generated by the microcontroller?

[kaushiks]

In the open drain configuration, is the PMOS Transistor present or not. If present, how is it made inactive even when the input is 0?

[samuwall]

At 1:56 I don't understand how the P-MOS can be activated by the 1. If '1' is logic high (3.3V/Vcc), then the voltage of the gate relative to the source (Vgs) is simply 0, and the P-MOS is not conductive. To activate the P-MOS, Vgs needs to be negative -- that is, the gate voltage would need to be logic low (0V/GND) while the source voltage is 3.3V/Vcc, meaning Vgs = -3.3V.

And again, at 2:21, if there is 0V on the gate of the P-MOS, the P-MOS will activate due to the negative Vgs, which means both mosfets will activate and Vcc and GND will be 'shorted' by the connected drains.

What am I missing?

[bobweiram]

Open drain is useful for certain bus applications.

[jonahst.hilaire]

Why is the output pulled to ground when a gate voltage is applied and nothing is connected to drain?

[cthutu]

So open drain with a pull up is just an inverter?

[jashwanthgoud]

There is a mistake at 2:34 pmos gate should be 1 not zero due to 1 it will turnoff

[itsme.]

1:03 The diagram has some mistake. The output Gate should not connect to both the PMOS and the NMOS. There should be 2 different gates connecting to different MOS. Otherwise, you could not get the desired control result.

[kelofu]

Nice try and pictures but it would be much clearer for beginners not to use a PMOS transistor with Gate inverter. Instead, I would draw an external one.

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[ИгорьБасов-ер]

Какой ужасный акцент, у меня кровь из ушей идет... -_-