3T DRAM- circuit, read and write operations

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𝗗𝗢𝗪𝗡𝗟𝗢𝗔𝗗 𝗦𝗵𝗿𝗲𝗻𝗶𝗸 𝗝𝗮𝗶𝗻 - 𝗦𝘁𝘂𝗱𝘆 𝗦𝗶𝗺𝗽𝗹𝗶𝗳𝗶𝗲𝗱 (𝗔𝗽𝗽) :

𝗙𝗢𝗟𝗟𝗢𝗪 𝗠𝗘 𝗢𝗡:

𝗦𝗨𝗕𝗦𝗖𝗥𝗜𝗕𝗘 𝗧𝗢 𝗠𝗬 𝗬𝗢𝗨𝗧𝗨𝗕𝗘 𝗖𝗛𝗔𝗡𝗡𝗘𝗟𝗦:

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gazab 6T SRAM, 3T DRAM, 1T DRAM covered my syllabus of gate(Semiconductor memories (digital electronics thanks

shanusingh

very simple and perfect explanation we need these teacherss

aniketrajapure

Bro my exam is in 2 hrs u made this topic so simplified this helped me a lot thank u so much

PruthvikaR-tm

u jst saved my life.. ive exam tomorrow u explained my half of the syllabus in 15 min.... thanks a lot dude

durgae

Instead of drawing the circuit before hand you should draw it while explaining the circuit. It helps in remembering it.

anurondas

Thank you for your detailed Explination

VishwanathgoudgOUD

too cool bro..thank you ..i can write my internals now

roopali

Thanks bro lec was awesome ur teaching is very good😎😎😎😍😍 thanks bro I was trying to understand this topic from hrs but not but from ur video I have understood thank u

ashishagrawal

Good explanation bro, but can u plz tell me steps to design dynamic ram cell (like using 4, 2 transistor) instead of

mcxsaikumar

Thanks buddy 🙏🏻 .You again saved my ass, tomorrow in my vlsi exam
Thanks a alot

vaibhavvalandikar

Can you explain the 4T DRAM using CMOS logic

nahiduzzamansojib

Isn't the threshold voltage only applicable in Gate voltage? I've learnt something new but who knows if it's right or wrong?

chiragarora

why would m1 need to be on... if it is already on due to word line being active 3:07

tabishkhatib

@4:53 you said bit bar will be forced because of bit, but as R=0 no current no voltage will be passed toh vo related kaise Hain??

yashgupta

Here in 3T DRAM for write operation you explained that X = Vdd - Vtn but why you didn't explain same thing for 1T DRAM? ... Am I missing something ? Why it is confusing me ?

niharikamodi

It is an excellent explanation. Can you please upload the detailed explanation of 4T DRAM ?

KamrulHasan-zgov

thank you sir try to give how it is working on layout point of view also with complete architecture of dram please

sahajapinky

is 3t-DRAM cell patented? Do you have to pay royalties?

absolute___zero

6:15: why capacitor(c2) will discharge if m2 and m3 are in on state?

sarfarazahmedsuri

y u were not telling threshold concept in 1 transsistor DRAM?could u expalain that, if u know?

RAJU-olcp

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