LENGTH OF DIFFUSION (LOD) - English Version

[analoglayout]

It is in fact not the gate voltage but the gate-source voltage. In 90nm, your supply is perhaps 1.2v, In the inverter case, the pmos source is connected to the supply. If gate is also connected to the supply, then you don't attract any holes to form the channel because Vgs=0. Start lowering gate towards 0V. When gate goes about 0.35V below source (Vg=0.85V), or gate is negative with respect to source or Vgs=-0.35V then you have certain amount of holes already attracted under the gate and the transistor is just about to start conducting. If you lower gate voltage even further, the channel becomes "fatter" and the transistor conducts stronger. If the drain of the pmos is connected to the drain of an nmos which is turning off at the same time like in the inverter, then the stronger you turn on the pmos, the weaker the nmos becomes - in other words pmos wants to conduct current but nmos opposes it. When nmos is off, the pmo current cannot flow anymore and the only possibility is for the drain of the pmos to become equal to the pmos source voltage, because current is 0 for Vds=0.
If you're doing circuits, I recommend that you learn device physics well, but then keep it at the back of your mind while you only use the concepts of current, voltage and charge to analyse the circuit operation. If for every circuit you start thinking in terms of holes and electrons, things become very complicated and this is not an useful approach.

[aniln]

Sir, u r really doing good videos. Thank you very much. I have one doubt on this. Please tell how did u get 2x drain n 1x source. If u split a transistor, u should get 2x drain n 2x source.

[swathisareddy]

Hi, your lectures are so good. Many people will get benefit from these lectures. I have one question that, in LOD topic why you are considering 2 drains at a time. If we will see cross sectional view OD continuation will not be there under poly. And 2nd till i thought LOD effect is due to stress around it's edges. due to that OD may shrink or extend little bit. to insert dummy we can avoid this problem.

[bharammr]

Thank you for ur excellent lecturing sir am learning a lot from u.
And in this LOD concept still i am not clarified with that change in Vth i.e increase and decrease of Vth, and also hou is drain area is increasing? could u please explain it clearly in next vedios..If possible....

[venkateshnandyala]

Sir i have doubt, Plsss give me reply....
In this video (please check time at 13:24) you explained that..In P-mos majority carriers are holes....
My doubt is.... You showing the N-WELL and you telling like holes are majarity carriers in N-WELL.
I think electrons are the majarity carrier's in n -well.
Pls clear my doubt 🙏🙏🙏🙏🙏

[-ES-AnushaB]

How do we consider the drain of g1 in the source of the g2

[bhanukallepalli]

Thanks for the explanation.. I have few doubts..
1. about vt change in pmos and nmos.. why it is different for these two types, means for pmos vt is decreasing and for nmos it is increasing right?
2. when you say that charge carriers are increasing in pmos/nmos are you referring to ions in substrate/well or diffusions(S/D)?
please help me understand this. Thank you..

[pravallikachebolu]

How drain area is more than source? And why we have double drains can u explain briefly?

[yuvrajsingh-oyop]

This LOD effect can also be called STI effect. So, whenever there is a diffusion break STI will be there which puts stress on our active devices and changes their Vt.
According to me to reduce this effect we can merge the active devices and put some dummies at the edges so that STI won't effect the devices at the edges and the devices in the center experience no STI/LOD effect as there is no diffusion break.
Am I wrong here? If yes, plz help me to get this concept?

[jainisri]

Hi sir am not understanding while doing fingering how drain area is doubled comapred to source area could you please clarify this one. Please upload STI effect video also . I am learning so many things from your lectures
Thank you so much ..

[vijaykumarsiddabathula]

How a single transistor have two drains, two fingers means 2 sources & 2 drains will present either s or d will be shared then how LOD occurs

[sangekum]

Sorry I think the LOD effect is actually based on the distance of active regions from STI i found this video quiet confusing...

[shwetatiwari]

Thanku sir ... For sharing knowledge .. it's too helpful. Bcoj of your vedio i got intrest in analog layout and many concept become clear

Again tqsm..👍

[sahajapinky]

sir can you explain about shallow trench isolation also please sir

[praveenreddy]

The videos your uploading is helping me a lot...can u please upload the videos about basic interview questions about layout enngr and also ESD TOPIC and sir tell me in BGR why we use bjts instead of fet ..I failed to answer this question in my interview

[paavammedias]

Sir u explained dd sharing is good. Because drain is collecting the current. I agree that. What about in MMOs the source is collecting the current. So ss sharing is good in nmos?

[bhavanavalaboju]

Thank you for the video sir. While doing layout, we usually fix LOD only for PMOS (by adding a dummy device). Why is it not fixed for NMOS?

[srinathkv]

Hello Sir, videos are well articulated.
Also request to add video on Poly space effect.

[moazhussain]

Thanks alot for clarification of LOD. Hats Off.

[sanjayreddy]

how drain area is 2x, cannot understand the diagram, if we have two fingers than we have source area 2x and drain area x