Introduction to cycle-accurate Verilog simulation, Dr Graham Markall (OSHCamp 2018)

Developing hardware designs in Verilog is tricky, for both FPGA platforms and ASIC hardware targets. Understanding the behaviour of a design, testing it, and debugging are made much easier by simulating in software. There are a variety of simulation approaches with different trade-offs in what properties of the design are accurately modelled and how quickly they run. This talk starts by giving a brief overview of the approaches, then focusing in more detail on cycle-accurate modelling, which is a relatively fast approach that is robustly implemented in an open-source tool called Verilator. The main focus will be on working with CPU designs, but the software and techniques are generally applicable to other areas.

A brief overview of how to use Verilator to simulate a design, to develop testbenches, and to visualise simulation output using GTKWave will be given. The software and techniques discussed in this talk will be put into practice in the "Open-source RISC-V core quickstart" workshop on Sunday.

Dr Graham Markall has a background in languages and compilers for scientific computing, and is well known for his work on the Numba project. He is part of Embecosm’s GNU tool chain team, where his current projects include the implementation of security enhancements to the GCC and LLVM compilers for RISC-V and ARM, and the development a GCC-based toolchain for a customised RISC-V processor.