Altium Designer RF Impedance Matching (e.g. 50Ω, USB, ...)

In this video I will show you how to use Altium Designer to create controlled impedance traces for your specific board stackup. This will enable you to have impedance matched networks on your board.

I will show you how to calculate track widths and gaps for single-ended and differential pairs.

[PlanGIV]

Very good stuff! Many thanks, that helps a lot ! 🙇‍♂

[Choober]

You just made a subject I've been trying to get my head round for ages, so simple, I can't understand why I couldn't get my head around it a lot earlier.

You explain things VERY well. Subbed.

[knechtnoobrecht-c]

Thanks for the video.
As far as i know, impedance depends on the signal's frequency. I've read that Altium assumes a frequency of 1GHz for its calculations, but my signal is 1590MHz. Where do i tell Altium this?

[abderraouflalla]

Very informative video. Just one question, does the length of the transmission line affects the impedance? Why the length effect of the wire is neglected?

[LefebvreSam]

If you have a double layer PCB and you want to create the copper plane with a polygon pour, do you need to create an additional rule to ensure that return path under the differential line is solid? Why you cannot select differential pair (classes) in the return path rule?

[DannyBokma]

Is there a way to have a more elegant way (narrower traces to be able to acces neighbor pins of the package as well) to enter into the IC package in your example?

[sir]

At what frequencies and boud rates we need to start thinking about lines impedances?

[saurabhjha]

Good, but at the IC pins we will get error of pin to trace clearance, should we need to make trace thinner at the IC, source ? Or just proceed with thinner differential tracks of ICs pad size.

[Andreasonline]

regarding the bottom reference. if you have a 4 layer stackup of sig/pow gnd gnd sig/pow.
from what i understand its a reference to the gnd plane which in this case is the top two and then for the bottom two on the other side.

the idea of a reference plane throws me off a little, is that correct ?

[HamzaKhan-esfi]

I am confused because the Top and Bottom layers are 1/2oz copper and the middle layers are 1oz copper. Usually its the other way around.

[sijo]

I have one doubt. Suppose if we use 3rd layer as reference of 1st top layer. Second copper layer are open in that area…Then while calculation, two dielectric and middle copper layer Thickenss and 2 dielectric Er should be added? Eg Dielectric er is 4.8 then the total er = 4.8+4.8 And thickness of dielectric is 0.2 and copper layer is 0, 35 mm then total thickness. Is 0.2+.035+0.2 ? Am I correct?

[iepNguyen-reii]

sorry.what used of document in this video.can you share it? thankyou.

[whiteking]

How bout the electrical line length or physical length of the trace, doesn't it affect the impedance of 90ohm meaning it can be of any length we don't care?

[jyreprejoles]

Sir do you have a video on smartphones Bluetooth antenna? Thank you

[parthasarathimishra]

No matching components (indictors, capacitors, pi-match etc) needed if we do the coplanar waveguide approach?

[High_Altitude_Observer]

Which version of Altium are you using? Thanks.