TSMC FinFlex: How Chips are made Worse to get Better

A deep-dive into FinDepopulation & TSMCs FinFlex technology. How the height of transistors is keeping Moore's Law alive.

0:00 Intro
0:50 NMOS, PMOS & CMOS Transistors
3:34 3D FinFETs & Transistor Height
6:48 Logic Gates & Standard Cells
9:54 Process Node Cell Libraries
13:31 How Fin Depopulation works
14:48 FinFET Process Node Scaling
18:34 TSMC FinFlex & Standard Cell Height
23:22 The future of chip design

[Benis]

I'm an engineer working in the semiconductor industry, and before clicking on this video, I didn’t have any particular expectations. However, your explanation turned out to be far more comprehensive and easy to understand than I anticipated—truly excellent. You covered everything from the basic semiconductor component structure to logic gates, IC design and layout concepts, and even introduced fundamental semiconductor manufacturing processes. This is a fantastic and impressive introduction to semiconductor manufacturing, perfect for newcomers interested in the industry. Well done

[oberguga]

In short words.
FinFets allow transistor to grow upward, so manufacturers start to reduce planars surface of transistors, but compensate it by making it taller.

[someasiandude]

programmers rather buy a processor that could simulate the entire universe than optimize their code for lower end hardware

[auritro]

As a high school teen who is really interested in CPU and transistor design, this channel seems like a perfect start for me and my semiconductor journey. Your explanations are clear, concise and engaging. I would love to see more such videos in the future :) <3

[AnonyMous-gtvq]

Let me issue another, very important correction.
Using a larger standard cell does NOT enable a higher clock speed. In fact, fore every application the optimal size standard cell is used, which minimizes power consumption. Today, this is calculated automatically, based on standard cell datasheet.
The condition used to calculate this is called fan out and is basically to how many standard cell inputs does the output of the previous cell connect. So for more connection a larger cell must be used, otherwise the rise and fall time of the signal will be slow, increasing the switching losses.
To control the actual speed of the standard cell, different voltage treshold cells are used. Low treshold cells for example will be faster than high treshold cells. Further there are high and low power cells available, both have then also several different voltage treshold variations. Finally all the different types of cells come in different sizes, so the appropriate size can always be chosen.

[spicybaguette]

Great explainer! One minor nitpick: CMOS in ICs is not really about creating a transistor from an NMOS and PMOS transistors, it's about using both NMOS and PMOS in a logic gate. CMOS is more power-efficient because it complements PMOS and NMOS circuits in the logic gate, so that pull-up and pull-down resistors are not needed (hence the name).The logic diagram of a NAND gate you showed already visualizes how this works: you have a pull-up circuit (the top one) consisting of two PMOS transistors in parallel, which pull up the output line when either of the input voltages is low. Then you have the pull-down circuit which pulls down the output line when both input voltages are high.

Generally, p-type transistors are used in pull-up and n-type in pull-down if I recall correctly, though I don't remember why.

Also, larger logic gates are not necessarily used for high performance or higher frequency. Like you said, they provide more current, but they are selected based on multiple criteria. For example the fan-out, which is the amount of logic gates that it needs to power. A larger logic gate consumes more power when switching, which can actually be detrimental at higher clock rates. Different size alternatives of logic gates are selected automatically by EDA software and used interchangeably

[mariobombo]

This is one of the best explanation of finflex - youtube algorithm should really pick up and spread this video.

[KingofArsenal]

This type of content, is why I fell in love with YouTube, information like this is very rare, so thank you sir, your channel will becomes huge! Just keep this up!

[joechang]

a transistor has two properties each with two possible conditions. One is N and P type as you said
the other is depletion and enhancement mode.
In depletion, the channel is on at zero gate voltage, gate voltage is required to turn on.
Enhancement mode, channel is off w/o at 0 gate voltage, and on with

[nviorres]

Amazing video, explaining a complex topic in 25 minutes in a way that someone without and relevant knowledge can understand.

[shigaraja]

this is basically the concept of "don't build out, build up." that led to the idea of Skyrises. so instead of taking up more area these transistors are taking up more volume. which will in turn lead to smaller but thicker chips with at least the same performance. it is better optimizations of the space that is already there but ultimately it is still limited as i would assume that there is a physical limit to how high these fins can be before they become too fragile.

[AnonyMous-gtvq]

Let me just give a small correction to the video.
There are two types of transistors, both of p and for n type.
They are called enchancement mode and depletion mode transistors. This refers to wether the transistors are on or off for zero gate voltage.
For the n mos, enchancement mode transistor, which is described in the video indeed a positive gate voltage is required to open it. For the depletion mode transistor, however, it will be open even at 0 gate voltage. Positive gate voltage will attract even more electrons, opening it more, while negative gate voltage will repel the electrons, closing it.
This type of transistor is rare and only used for high frequency analog application.
For the p type it is similar. A negative voltage on the gate will attract electron holes, which are positively charged. A positive voltage will repel the holes, closing the transistor.
In a depletion mode transistor the holes are already present at zero gate voltage, forming the channel.

[devbites]

I really like your clear and concise teaching style for this complex topic. It was fascinating to hear about the tech. Even though I'm mostly software focused, I have a strong interest in micro-electronics, and circuit design.

[MFMegaZeroX]

Yay, a new High Yield video! And thanks for pointing out Ken Sheriff's blog, I'll definitely want to give it a read sometime.

[AdvantestInc]

The idea of "making a chip better by making it worse" through fin depopulation is both counterintuitive and fascinating, great explanation!

[Drumaier]

I'm constantly reading and watching videos about this topic, just because I'm a little nerd and this nano technology and logic things related to chip manufacturing blows my mind. I try to understand about all this but is too complex and I lack basic education about electricity to start with (I'm just a 3d artist). BUT, this video was different, I'm leaving with the impression of undertanding some things at least. For example I didn't know CMOS meant P and N transistors toguether, didn't know that you can compensate less fins with taller ones....and seeing the animations now I understand better in which direction the current flow (I have it flipped in my head 😅🤡). So, thanks a lot for this video, is really making a big difference for me. I'd love to see more of this videos in which you explain more of this things, a "chip design for dummies" series would be soooo cool.

[zmm]

The ability to parse such technology into our brain is on itself a remarkable technology, brilliant video Mr. Yield.

[VADemon]

I finally finished the video. It's incredibly easy to follow for a deep topic I knew nothing about. Kudos

[zblurth]

I feel like I should have paid to see something that well explained

[miinyoo]

Neat! Someone finally clearly explained Cell Height and why transistors are set up in groups rather than individually.